Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1608511	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36536986

1

T1

350

T2

5204

T3

2789

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26151404	1			T1	175		T2	1994		T3	362
values[0x0]	10566477	1			T1	175		T2	3210		T3	2427
values[0x1]	1427616	1			T1	3		T2	280		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	419787	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37725710

1

T1

353

T2

5484

T3

2811

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18152824	1			T1	177		T2	2742		T3	1406
valid_sources[0x01]	18151885	1			T1	176		T2	2742		T3	1405
valid_sources[0x02]	29616	1			T37	2		T59	2		T229	2
valid_sources[0x03]	29577	1			T59	1		T97	3		T884	1
valid_sources[0x04]	30021	1			T37	1		T97	1		T227	1
valid_sources[0x05]	29427	1			T59	2		T97	1		T229	7
valid_sources[0x06]	29547	1			T37	1		T59	2		T884	9
valid_sources[0x07]	30026	1			T59	1		T229	4		T884	9
valid_sources[0x08]	29369	1			T884	8		T170	81		T404	17
valid_sources[0x09]	29605	1			T229	4		T170	57		T404	21
valid_sources[0x0a]	29091	1			T59	1		T170	78		T404	23
valid_sources[0x0b]	29759	1			T59	1		T97	1		T227	2
valid_sources[0x0c]	29951	1			T59	2		T170	73		T404	29
valid_sources[0x0d]	29238	1			T884	2		T170	78		T404	20
valid_sources[0x0e]	29023	1			T59	2		T227	1		T884	3
valid_sources[0x0f]	36064	1			T37	4		T97	2		T227	1
valid_sources[0x10]	29174	1			T59	1		T227	1		T229	1
valid_sources[0x11]	29540	1			T227	2		T884	2		T170	99
valid_sources[0x12]	29827	1			T37	1		T59	1		T884	3
valid_sources[0x13]	29912	1			T37	1		T59	3		T97	1
valid_sources[0x14]	29813	1			T37	1		T97	1		T227	1
valid_sources[0x15]	30303	1			T59	3		T227	1		T884	7
valid_sources[0x16]	29442	1			T37	1		T884	9		T170	76
valid_sources[0x17]	29054	1			T37	2		T227	1		T228	39
valid_sources[0x18]	29333	1			T37	1		T170	83		T404	26
valid_sources[0x19]	29113	1			T37	1		T97	2		T227	1
valid_sources[0x1a]	29412	1			T227	1		T884	5		T170	92
valid_sources[0x1b]	29043	1			T227	1		T884	6		T170	67
valid_sources[0x1c]	28985	1			T97	1		T884	2		T170	67
valid_sources[0x1d]	29771	1			T97	1		T227	1		T229	1
valid_sources[0x1e]	29868	1			T227	1		T884	1		T170	81
valid_sources[0x1f]	29415	1			T37	4		T227	2		T229	2
valid_sources[0x20]	29636	1			T59	2		T884	2		T170	75

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25746669

1

T1

175

T2

1994

T3

362

values[0x0]

all_enables

biggest_size

10510973

1

T1

175

T2

3210

T3

2427

values[0x1]

all_enables

biggest_size

279344

1

T37

20

T59

15

T97

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2906559	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

458587

1

T94

28

T95

12

T96

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1140487	1			T94	62		T95	42		T96	47
values[0x0]	1084573	1			T94	59		T95	56		T96	50
values[0x1]	1140086	1			T94	68		T95	51		T96	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2250745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1114401

1

T94

72

T95

32

T96

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52864	1			T95	6		T96	2		T158	1
valid_sources[0x01]	51761	1			T94	4		T95	5		T96	4
valid_sources[0x02]	52920	1			T94	8		T96	3		T98	15
valid_sources[0x03]	51058	1			T95	3		T98	9		T158	2
valid_sources[0x04]	52791	1			T94	4		T95	1		T98	19
valid_sources[0x05]	53239	1			T94	4		T95	2		T98	9
valid_sources[0x06]	52804	1			T94	8		T95	3		T96	22
valid_sources[0x07]	52681	1			T95	2		T96	2		T98	17
valid_sources[0x08]	51746	1			T95	4		T158	1		T177	5
valid_sources[0x09]	53074	1			T94	3		T95	2		T158	1
valid_sources[0x0a]	51750	1			T94	5		T95	1		T177	1
valid_sources[0x0b]	53673	1			T95	1		T177	4		T570	3
valid_sources[0x0c]	53737	1			T94	9		T95	2		T570	15
valid_sources[0x0d]	52419	1			T95	4		T177	3		T570	9
valid_sources[0x0e]	51922	1			T94	5		T95	4		T96	2
valid_sources[0x0f]	52409	1			T94	1		T95	1		T177	1
valid_sources[0x10]	52188	1			T94	1		T95	4		T96	3
valid_sources[0x11]	51884	1			T95	1		T96	15		T177	2
valid_sources[0x12]	52194	1			T94	5		T95	3		T98	17
valid_sources[0x13]	52465	1			T94	4		T95	1		T177	2
valid_sources[0x14]	53447	1			T94	2		T95	4		T177	1
valid_sources[0x15]	52729	1			T94	3		T95	7		T98	29
valid_sources[0x16]	52699	1			T94	8		T95	6		T158	3
valid_sources[0x17]	52044	1			T94	5		T95	3		T177	2
valid_sources[0x18]	53204	1			T94	3		T95	2		T98	20
valid_sources[0x19]	52882	1			T94	8		T95	4		T96	9
valid_sources[0x1a]	53675	1			T94	3		T95	1		T158	1
valid_sources[0x1b]	52572	1			T94	4		T177	3		T570	7
valid_sources[0x1c]	52438	1			T94	9		T95	1		T98	14
valid_sources[0x1d]	53816	1			T94	3		T95	2		T158	1
valid_sources[0x1e]	52094	1			T94	1		T95	5		T177	1
valid_sources[0x1f]	52048	1			T94	3		T177	2		T570	12
valid_sources[0x20]	52967	1			T94	2		T95	2		T158	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48603

1

T94

1

T95

1

T96

2

values[0x0]

all_enables

biggest_size

361724

1

T94

23

T95

9

T96

14

values[0x1]

all_enables

biggest_size

48260

1

T94

4

T95

2

T96

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3099052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

504830

1

T94

12

T95

20

T96

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1234716	1			T94	40		T95	63		T96	29
values[0x0]	1136126	1			T94	39		T95	43		T96	41
values[0x1]	1233040	1			T94	47		T95	52		T96	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2377548	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1226334

1

T94

34

T95

59

T96

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56703	1			T94	1		T96	2		T177	3
valid_sources[0x01]	55814	1			T94	1		T96	4		T98	18
valid_sources[0x02]	57251	1			T94	2		T95	3		T98	11
valid_sources[0x03]	56513	1			T94	5		T96	2		T98	11
valid_sources[0x04]	57189	1			T94	2		T95	13		T96	2
valid_sources[0x05]	56170	1			T94	3		T95	2		T98	16
valid_sources[0x06]	55966	1			T94	1		T96	3		T177	5
valid_sources[0x07]	56541	1			T94	6		T96	2		T98	19
valid_sources[0x08]	56323	1			T96	1		T158	1		T177	7
valid_sources[0x09]	56757	1			T94	3		T96	1		T177	2
valid_sources[0x0a]	56813	1			T94	2		T95	3		T96	2
valid_sources[0x0b]	56468	1			T94	1		T96	3		T158	1
valid_sources[0x0c]	56745	1			T94	1		T95	3		T96	1
valid_sources[0x0d]	55924	1			T95	1		T96	3		T158	1
valid_sources[0x0e]	55781	1			T94	2		T96	1		T177	8
valid_sources[0x0f]	56594	1			T94	6		T96	1		T158	1
valid_sources[0x10]	57068	1			T94	5		T95	4		T96	1
valid_sources[0x11]	55743	1			T94	2		T95	15		T96	2
valid_sources[0x12]	56602	1			T96	1		T98	29		T158	1
valid_sources[0x13]	57118	1			T94	1		T158	1		T177	3
valid_sources[0x14]	56104	1			T94	1		T177	2		T570	9
valid_sources[0x15]	54822	1			T96	2		T98	33		T158	1
valid_sources[0x16]	56172	1			T94	2		T95	25		T96	4
valid_sources[0x17]	56416	1			T94	1		T96	2		T177	1
valid_sources[0x18]	55842	1			T94	4		T95	2		T96	8
valid_sources[0x19]	56540	1			T94	2		T95	6		T96	5
valid_sources[0x1a]	56866	1			T94	2		T95	1		T96	1
valid_sources[0x1b]	55937	1			T94	2		T95	20		T96	1
valid_sources[0x1c]	54984	1			T94	2		T95	6		T98	15
valid_sources[0x1d]	57236	1			T94	4		T96	1		T177	1
valid_sources[0x1e]	56909	1			T94	1		T96	1		T177	3
valid_sources[0x1f]	56250	1			T94	1		T95	1		T96	2
valid_sources[0x20]	55561	1			T94	4		T96	4		T177	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53175

1

T94

2

T95

3

T96

1

values[0x0]

all_enables

biggest_size

398831

1

T94

10

T95

15

T96

16

values[0x1]

all_enables

biggest_size

52824

1

T95

2

T96

2

T98

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2927627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

463598

1

T94

21

T95

20

T96

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1150054	1			T94	48		T95	38		T96	67
values[0x0]	1092010	1			T94	53		T95	38		T96	57
values[0x1]	1149161	1			T94	44		T95	33		T96	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2266638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1124587

1

T94

44

T95

40

T96

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53102	1			T96	4		T177	5		T570	11
valid_sources[0x01]	53234	1			T96	3		T98	8		T177	5
valid_sources[0x02]	53524	1			T96	5		T98	20		T177	3
valid_sources[0x03]	52338	1			T95	1		T96	5		T98	11
valid_sources[0x04]	52775	1			T94	3		T96	2		T98	8
valid_sources[0x05]	52905	1			T95	2		T96	2		T98	13
valid_sources[0x06]	52134	1			T95	4		T96	7		T177	6
valid_sources[0x07]	53000	1			T95	2		T96	5		T98	11
valid_sources[0x08]	52651	1			T96	2		T177	1		T570	8
valid_sources[0x09]	53384	1			T96	5		T158	1		T177	1
valid_sources[0x0a]	52889	1			T96	1		T158	1		T177	3
valid_sources[0x0b]	53206	1			T94	17		T96	5		T158	1
valid_sources[0x0c]	51598	1			T96	3		T158	1		T177	2
valid_sources[0x0d]	52633	1			T96	1		T158	1		T177	9
valid_sources[0x0e]	52855	1			T94	2		T95	1		T96	2
valid_sources[0x0f]	53120	1			T96	3		T177	4		T570	12
valid_sources[0x10]	53286	1			T94	5		T96	1		T177	1
valid_sources[0x11]	53789	1			T95	9		T96	1		T177	1
valid_sources[0x12]	53422	1			T96	1		T98	28		T177	1
valid_sources[0x13]	52513	1			T96	3		T177	1		T570	15
valid_sources[0x14]	52731	1			T96	4		T158	1		T177	4
valid_sources[0x15]	52268	1			T95	6		T96	1		T98	27
valid_sources[0x16]	52688	1			T96	4		T177	3		T570	10
valid_sources[0x17]	52030	1			T95	5		T96	5		T177	2
valid_sources[0x18]	52868	1			T96	5		T98	5		T177	2
valid_sources[0x19]	53516	1			T94	7		T95	1		T96	2
valid_sources[0x1a]	53001	1			T94	3		T96	1		T177	1
valid_sources[0x1b]	52608	1			T96	5		T177	2		T570	18
valid_sources[0x1c]	52056	1			T94	2		T96	3		T98	14
valid_sources[0x1d]	53423	1			T95	3		T96	2		T177	3
valid_sources[0x1e]	53490	1			T95	1		T96	2		T570	19
valid_sources[0x1f]	52239	1			T95	3		T96	3		T158	2
valid_sources[0x20]	52423	1			T94	2		T96	2		T177	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49138

1

T94

2

T95

1

T98

1

values[0x0]

all_enables

biggest_size

365345

1

T94

17

T95

16

T96

16

values[0x1]

all_enables

biggest_size

49115

1

T94

2

T95

3

T96

1