Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_filter
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter 59.84 63.64 44.44 71.43
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter 59.84 63.64 44.44 71.43
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter 59.84 63.64 44.44 71.43
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter 91.53 100.00 88.89 85.71
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity 100.00 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset 100.00 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense 100.00 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter 100.00 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter 100.00 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter 100.00 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.84 63.64 44.44 71.43


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.58 76.47 44.44 81.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.52 52.63 38.46 45.45 gen_wkup_detect[1].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.84 63.64 44.44 71.43


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.58 76.47 44.44 81.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.52 52.63 38.46 45.45 gen_wkup_detect[4].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.84 63.64 44.44 71.43


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.58 76.47 44.44 81.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
33.85 42.11 23.08 36.36 gen_wkup_detect[6].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.53 100.00 88.89 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 88.89 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
61.50 68.42 61.54 54.55 gen_wkup_detect[2].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.98 100.00 93.18 94.74 100.00 u_usbdev_aon_wake


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.98 100.00 93.18 94.74 100.00 u_usbdev_aon_wake


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.98 100.00 93.18 94.74 100.00 u_usbdev_aon_wake


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.33 78.95 92.31 72.73 gen_wkup_detect[0].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
64.07 68.42 69.23 54.55 gen_wkup_detect[3].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
64.07 68.42 69.23 54.55 gen_wkup_detect[5].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
59.28 63.16 69.23 45.45 gen_wkup_detect[7].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T2 T3 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T2 T3 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T2 T3 
Cond Coverage for Module : prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Module : prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL11763.64
ALWAYS4844100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
ALWAYS5933100.00
CONT_ASSIGN66100.00
CONT_ASSIGN70100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                   ==>  MISSING_ELSE
53                        end
54                      
55         0/1     ==>    assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
56         0/1     ==>    assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         0/1     ==>    assign update_stored_value =
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         0/1     ==>    assign filter_o = enable_i ? stored_value_q : filter_synced;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 70 2 1 50.00
IF 48 3 2 66.67
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL11763.64
ALWAYS4844100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
ALWAYS5933100.00
CONT_ASSIGN66100.00
CONT_ASSIGN70100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                   ==>  MISSING_ELSE
53                        end
54                      
55         0/1     ==>    assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
56         0/1     ==>    assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         0/1     ==>    assign update_stored_value =
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         0/1     ==>    assign filter_o = enable_i ? stored_value_q : filter_synced;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 70 2 1 50.00
IF 48 3 2 66.67
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL11763.64
ALWAYS4844100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
ALWAYS5933100.00
CONT_ASSIGN66100.00
CONT_ASSIGN70100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                   ==>  MISSING_ELSE
53                        end
54                      
55         0/1     ==>    assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
56         0/1     ==>    assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         0/1     ==>    assign update_stored_value =
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         0/1     ==>    assign filter_o = enable_i ? stored_value_q : filter_synced;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 70 2 1 50.00
IF 48 3 2 66.67
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T27 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T27 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T27 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T27 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT27
01CoveredT27
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT27
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 70 2 1 50.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T27 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T2 T3 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T2 T3 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T7 T35 T9 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T7 T35 T9 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T7 T35 T9 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T7 T35 T9 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT7,T35,T9
01CoveredT7,T35,T9
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT7,T35,T9
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T35,T9 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T7,T35,T9 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T2 T3 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T2 T3 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T2 T6 T13 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T2 T6 T13 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T2 T6 T13 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T2 T6 T13 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT2,T6,T13
01CoveredT2,T6,T13
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT2,T6,T13
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T13 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT59
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Covered T59
0 Covered T1,T2,T3 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T2,T6,T13 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T59 T26 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T59 T26 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T59 T26 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T59 T26 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT59,T26
01CoveredT59,T26
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT59,T26
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT59,T26 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT59
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Covered T59
0 Covered T1,T2,T3 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T59,T26 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T70 T71 T59 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T70 T71 T59 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T70 T71 T59 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T70 T71 T59 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT70,T71,T59
01CoveredT70,T71,T59
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT70,T71,T59
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT70,T71,T59 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT59
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Covered T59
0 Covered T1,T2,T3 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T70,T71,T59 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T59 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T59 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T59 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T59 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT59
01CoveredT59
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT59
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT59 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT59
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Covered T59
0 Covered T1,T2,T3 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T59 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%