Unified Coverage Report :: Module :: gpio

Module : gpio

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_gpio	100.00			100.00

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Module Instance : tb.dut.top_earlgrey.u_gpio

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

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Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : gpio

	Total	Covered	Percent
Totals	33	33	100.00
Total Bits	540	540	100.00
Total Bits 0->1	270	270	100.00
Total Bits 1->0	270	270	100.00

Ports	33	33	100.00
Port Bits	540	540	100.00
Port Bits 0->1	270	270	100.00
Port Bits 1->0	270	270	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T43,T33,T38	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T37,*T59	Yes	T87,T37,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T59,T97	Yes	T37,T59,T97	INPUT
tl_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_error	Yes	Yes	T94,T98,T158	Yes	T94,T158,T177	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T30,T13,T329	Yes	T30,T13,T329	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T30,T13,T329	Yes	T6,T30,T13	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T30,T13,T329	Yes	T6,T30,T13	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T96,T158	Yes	T94,T158,T177	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T94,*T98,*T158	Yes	T94,T95,T96	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T96,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T43,*T30	Yes	T2,T3,T4	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
intr_gpio_o[31:0]	Yes	Yes	T30,T329,T41	Yes	T30,T329,T41	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T73,T99,T100	Yes	T73,T99,T100	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T73,T99,T100	Yes	T73,T99,T100	OUTPUT
cio_gpio_i[31:0]	Yes	Yes	T30,T13,T40	Yes	T30,T13,T40	INPUT
cio_gpio_o[31:0]	Yes	Yes	T6,T30,T51	Yes	T6,T30,T51	OUTPUT
cio_gpio_en_o[31:0]	Yes	Yes	T30,T41,T42	Yes	T6,T30,T13	OUTPUT

*Tests covering at least one bit in the range