Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500363577	59627226	0	0
DepthKnown_A	500363577	500258697	0	0
RvalidKnown_A	500363577	500258697	0	0
WreadyKnown_A	500363577	500258697	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	59627226	0	0
T1	42257	3485	0	0
T2	90239	12236	0	0
T3	57027	5188	0	0
T4	94235	11425	0	0
T5	106625	67061	0	0
T6	105989	13787	0	0
T7	79364	8756	0	0
T8	106091	11939	0	0
T10	83445	10050	0	0
T35	95978	10882	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500363577	45186090	0	0
DepthKnown_A	500363577	500258697	0	0
RvalidKnown_A	500363577	500258697	0	0
WreadyKnown_A	500363577	500258697	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	45186090	0	0
T1	42257	1880	0	0
T2	90239	8594	0	0
T3	57027	3520	0	0
T4	94235	8871	0	0
T5	106625	33130	0	0
T6	105989	9451	0	0
T7	79364	6256	0	0
T8	106091	9243	0	0
T10	83445	7252	0	0
T35	95978	8770	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500363577	43346240	0	0
DepthKnown_A	500363577	500258697	0	0
RvalidKnown_A	500363577	500258697	0	0
WreadyKnown_A	500363577	500258697	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	43346240	0	0
T1	42257	461	0	0
T2	90239	5654	0	0
T3	57027	2924	0	0
T4	94235	7576	0	0
T5	106625	7116	0	0
T6	105989	7100	0	0
T7	79364	3661	0	0
T8	106091	9122	0	0
T10	83445	5166	0	0
T35	95978	6419	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T37 T59 T97 
49         1/1              assign full_o = rready_i;
           Tests:       T37 T59 T97 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500363577	36329298	0	0
DepthKnown_A	500363577	500258697	0	0
RvalidKnown_A	500363577	500258697	0	0
WreadyKnown_A	500363577	500258697	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	36329298	0	0
T1	42257	353	0	0
T2	90239	5484	0	0
T3	57027	2811	0	0
T4	94235	7398	0	0
T5	106625	6455	0	0
T6	105989	6757	0	0
T7	79364	3525	0	0
T8	106091	8664	0	0
T10	83445	4994	0	0
T35	95978	6292	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500363577	500258697	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580363590	80626	0	0
DepthKnown_A	580363590	580242655	0	0
RvalidKnown_A	580363590	580242655	0	0
WreadyKnown_A	580363590	580242655	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	80626	0	0
T1	42257	8	0	0
T2	90239	24	0	0
T3	57027	13	0	0
T4	94235	24	0	0
T5	106625	34	0	0
T6	105989	41	0	0
T7	79364	13	0	0
T8	106091	208	0	0
T10	83445	18	0	0
T35	95978	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580363590	81734	0	0
DepthKnown_A	580363590	580242655	0	0
RvalidKnown_A	580363590	580242655	0	0
WreadyKnown_A	580363590	580242655	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	81734	0	0
T1	42257	8	0	0
T2	90239	24	0	0
T3	57027	13	0	0
T4	94235	24	0	0
T5	106625	34	0	0
T6	105989	41	0	0
T7	79364	13	0	0
T8	106091	208	0	0
T10	83445	18	0	0
T35	95978	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580363590	51780	0	0
DepthKnown_A	580363590	580242655	0	0
RvalidKnown_A	580363590	580242655	0	0
WreadyKnown_A	580363590	580242655	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	51780	0	0
T1	42257	8	0	0
T2	90239	21	0	0
T3	57027	12	0	0
T4	94235	23	0	0
T5	106625	31	0	0
T6	105989	38	0	0
T7	79364	12	0	0
T8	106091	205	0	0
T10	83445	15	0	0
T35	95978	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580363590	51780	0	0
DepthKnown_A	580363590	580242655	0	0
RvalidKnown_A	580363590	580242655	0	0
WreadyKnown_A	580363590	580242655	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	51780	0	0
T1	42257	8	0	0
T2	90239	21	0	0
T3	57027	12	0	0
T4	94235	23	0	0
T5	106625	31	0	0
T6	105989	38	0	0
T7	79364	12	0	0
T8	106091	205	0	0
T10	83445	15	0	0
T35	95978	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580363590	28846	0	0
DepthKnown_A	580363590	580242655	0	0
RvalidKnown_A	580363590	580242655	0	0
WreadyKnown_A	580363590	580242655	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	28846	0	0
T2	90239	3	0	0
T3	57027	1	0	0
T4	94235	1	0	0
T5	106625	3	0	0
T6	105989	3	0	0
T7	79364	1	0	0
T8	106091	3	0	0
T10	83445	3	0	0
T35	95978	1	0	0
T116	89158	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580363590	29954	0	0
DepthKnown_A	580363590	580242655	0	0
RvalidKnown_A	580363590	580242655	0	0
WreadyKnown_A	580363590	580242655	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	29954	0	0
T2	90239	3	0	0
T3	57027	1	0	0
T4	94235	1	0	0
T5	106625	3	0	0
T6	105989	3	0	0
T7	79364	1	0	0
T8	106091	3	0	0
T10	83445	3	0	0
T35	95978	1	0	0
T116	89158	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580363590	580242655	0	0
T1	42257	42199	0	0
T2	90239	90177	0	0
T3	57027	56969	0	0
T4	94235	94184	0	0
T5	106625	106570	0	0
T6	105989	105938	0	0
T7	79364	79309	0	0
T8	106091	106036	0	0
T10	83445	83387	0	0
T35	95978	95923	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T35	1	1	0	0