Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T59 T94 T95
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T59,T453,T426 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T170,T169,T171 |
| 1 | 0 | Covered | T426,T170,T582 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T59,T453,T426 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T59 T94 T95
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_1.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T59,T279,T548 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T170,T169,T174 |
| 1 | 0 | Covered | T559,T170,T582 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T59,T279,T548 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T205 T59 T269
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T205,T59,T269 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T205,T59,T269 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T205 T59 T269
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_1.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T205,T59,T269 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T205,T59,T269 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T205 T59 T269
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T205,T59,T269 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T205,T59,T269 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T205 T59 T269
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_1.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T205,T59,T269 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T205,T59,T269 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T205 T59 T269
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T205,T59,T269 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T205,T59,T269 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T205 T59 T269
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_1.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T205,T59,T269 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T59,T269 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T205,T59,T269 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_alert_en.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
59 // If both try to set/clr at the same bit pos, SW wins.
60 1/1 assign wr_en = we | de;
Tests: T43 T44 T81
61 if (Mubi) begin : gen_mubi
62 if (DW == 4) begin : gen_mubi4
63 assign wr_data = prim_mubi_pkg::mubi4_or_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
64 (we ? prim_mubi_pkg::mubi4_t'(wd) :
65 prim_mubi_pkg::MuBi4False));
66 end else if (DW == 8) begin : gen_mubi8
67 assign wr_data = prim_mubi_pkg::mubi8_or_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
68 (we ? prim_mubi_pkg::mubi8_t'(wd) :
69 prim_mubi_pkg::MuBi8False));
70 end else if (DW == 12) begin : gen_mubi12
71 assign wr_data = prim_mubi_pkg::mubi12_or_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
72 (we ? prim_mubi_pkg::mubi12_t'(wd) :
73 prim_mubi_pkg::MuBi12False));
74 end else if (DW == 16) begin : gen_mubi16
75 assign wr_data = prim_mubi_pkg::mubi16_or_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
76 (we ? prim_mubi_pkg::mubi16_t'(wd) :
77 prim_mubi_pkg::MuBi16False));
78 end else begin : gen_invalid_mubi
79 $error("%m: Invalid width for MuBi");
80 end
81 end else begin : gen_non_mubi
82 1/1 assign wr_data = (de ? d : q) | (we ? wd : '0);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_alert_en.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T43,T44,T81 |
LINE 82
EXPRESSION ((de ? d : q) | (we ? wd : '0))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T43,T44,T81 |
| 1 | 0 | Covered | T43,T44,T81 |
LINE 82
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Unreachable | |
LINE 82
SUB-EXPRESSION (we ? wd : '0)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T43,T44,T81 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_wdog_en.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
59 // If both try to set/clr at the same bit pos, SW wins.
60 1/1 assign wr_en = we | de;
Tests: T43 T44 T81
61 if (Mubi) begin : gen_mubi
62 if (DW == 4) begin : gen_mubi4
63 assign wr_data = prim_mubi_pkg::mubi4_or_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
64 (we ? prim_mubi_pkg::mubi4_t'(wd) :
65 prim_mubi_pkg::MuBi4False));
66 end else if (DW == 8) begin : gen_mubi8
67 assign wr_data = prim_mubi_pkg::mubi8_or_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
68 (we ? prim_mubi_pkg::mubi8_t'(wd) :
69 prim_mubi_pkg::MuBi8False));
70 end else if (DW == 12) begin : gen_mubi12
71 assign wr_data = prim_mubi_pkg::mubi12_or_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
72 (we ? prim_mubi_pkg::mubi12_t'(wd) :
73 prim_mubi_pkg::MuBi12False));
74 end else if (DW == 16) begin : gen_mubi16
75 assign wr_data = prim_mubi_pkg::mubi16_or_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
76 (we ? prim_mubi_pkg::mubi16_t'(wd) :
77 prim_mubi_pkg::MuBi16False));
78 end else begin : gen_invalid_mubi
79 $error("%m: Invalid width for MuBi");
80 end
81 end else begin : gen_non_mubi
82 1/1 assign wr_data = (de ? d : q) | (we ? wd : '0);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_wdog_en.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T43,T44,T81 |
LINE 82
EXPRESSION ((de ? d : q) | (we ? wd : '0))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T43,T44,T81 |
| 1 | 0 | Covered | T43,T44,T81 |
LINE 82
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Unreachable | |
LINE 82
SUB-EXPRESSION (we ? wd : '0)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T43,T44,T81 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_alert.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
87 // If both try to set/clr at the same bit pos, SW wins.
88 1/1 assign wr_en = we | de;
Tests: T43 T44 T81
89 if (Mubi) begin : gen_mubi
90 if (DW == 4) begin : gen_mubi4
91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92 (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93 prim_mubi_pkg::MuBi4True));
94 end else if (DW == 8) begin : gen_mubi8
95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96 (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97 prim_mubi_pkg::MuBi8True));
98 end else if (DW == 12) begin : gen_mubi12
99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100 (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101 prim_mubi_pkg::MuBi12True));
102 end else if (DW == 16) begin : gen_mubi16
103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104 (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105 prim_mubi_pkg::MuBi16True));
106 end else begin : gen_invalid_mubi
107 $error("%m: Invalid width for MuBi");
108 end
109 end else begin : gen_non_mubi
110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_alert.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T43,T44,T81 |
| 1 | 0 | Covered | T450,T69,T124 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T450,T451,T452 |
| 1 | 1 | Covered | T43,T44,T81 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T43,T44,T81 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T450,T69,T124 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_wdog.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
87 // If both try to set/clr at the same bit pos, SW wins.
88 1/1 assign wr_en = we | de;
Tests: T265 T266 T68
89 if (Mubi) begin : gen_mubi
90 if (DW == 4) begin : gen_mubi4
91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92 (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93 prim_mubi_pkg::MuBi4True));
94 end else if (DW == 8) begin : gen_mubi8
95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96 (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97 prim_mubi_pkg::MuBi8True));
98 end else if (DW == 12) begin : gen_mubi12
99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100 (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101 prim_mubi_pkg::MuBi12True));
102 end else if (DW == 16) begin : gen_mubi16
103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104 (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105 prim_mubi_pkg::MuBi16True));
106 end else begin : gen_invalid_mubi
107 $error("%m: Invalid width for MuBi");
108 end
109 end else begin : gen_non_mubi
110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_wdog.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T265,T266,T68 |
| 1 | 0 | Covered | T450,T69,T124 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T450,T69,T124 |
| 1 | 1 | Covered | T265,T266,T68 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T265,T266,T68 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T450,T69,T124 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_err_status_reg_intg_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
87 // If both try to set/clr at the same bit pos, SW wins.
88 1/1 assign wr_en = we | de;
Tests: T1 T2 T3
89 if (Mubi) begin : gen_mubi
90 if (DW == 4) begin : gen_mubi4
91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92 (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93 prim_mubi_pkg::MuBi4True));
94 end else if (DW == 8) begin : gen_mubi8
95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96 (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97 prim_mubi_pkg::MuBi8True));
98 end else if (DW == 12) begin : gen_mubi12
99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100 (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101 prim_mubi_pkg::MuBi12True));
102 end else if (DW == 16) begin : gen_mubi16
103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104 (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105 prim_mubi_pkg::MuBi16True));
106 end else begin : gen_invalid_mubi
107 $error("%m: Invalid width for MuBi");
108 end
109 end else begin : gen_non_mubi
110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_err_status_reg_intg_err.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 9 | 90.00 |
| Logical | 10 | 9 | 90.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T276,T277,T278 |
| 1 | 0 | Covered | T59,T429,T453 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T276,T277,T278 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T276,T277,T278 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T59,T429,T453 |