Module Definition
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Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.41 100.00 69.65 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.99 91.27 82.99 93.72 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.83 94.59 90.00 79.58 100.00 100.00 u_sensor_ctrl_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_en_0 100.00 100.00 100.00 100.00
u_alert_en_1 100.00 100.00 100.00 100.00
u_alert_en_10 100.00 100.00 100.00 100.00
u_alert_en_2 100.00 100.00 100.00 100.00
u_alert_en_3 100.00 100.00 100.00 100.00
u_alert_en_4 100.00 100.00 100.00 100.00
u_alert_en_5 100.00 100.00 100.00 100.00
u_alert_en_6 100.00 100.00 100.00 100.00
u_alert_en_7 100.00 100.00 100.00 100.00
u_alert_en_8 100.00 100.00 100.00 100.00
u_alert_en_9 100.00 100.00 100.00 100.00
u_alert_test_fatal_alert 100.00 100.00
u_alert_test_recov_alert 100.00 100.00
u_alert_trig_val_0 100.00 100.00 100.00 100.00
u_alert_trig_val_1 100.00 100.00 100.00 100.00
u_alert_trig_val_10 100.00 100.00 100.00 100.00
u_alert_trig_val_2 100.00 100.00 100.00 100.00
u_alert_trig_val_3 100.00 100.00 100.00 100.00
u_alert_trig_val_4 100.00 100.00 100.00 100.00
u_alert_trig_val_5 100.00 100.00 100.00 100.00
u_alert_trig_val_6 100.00 100.00 100.00 100.00
u_alert_trig_val_7 100.00 100.00 100.00 100.00
u_alert_trig_val_8 100.00 100.00 100.00 100.00
u_alert_trig_val_9 100.00 100.00 100.00 100.00
u_cfg_regwen 51.48 44.44 50.00 60.00
u_chk 100.00 100.00 100.00
u_fatal_alert_en_val_0 100.00 100.00 100.00 100.00
u_fatal_alert_en_val_1 100.00 100.00 100.00 100.00
u_fatal_alert_en_val_10 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_2 100.00 100.00 100.00 100.00
u_fatal_alert_en_val_3 100.00 100.00 100.00 100.00
u_fatal_alert_en_val_4 100.00 100.00 100.00 100.00
u_fatal_alert_en_val_5 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_6 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_7 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_8 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_9 96.30 88.89 100.00 100.00
u_fatal_alert_val_0 96.30 88.89 100.00 100.00
u_fatal_alert_val_1 96.30 88.89 100.00 100.00
u_fatal_alert_val_10 47.78 33.33 50.00 60.00
u_fatal_alert_val_11 96.30 88.89 100.00 100.00
u_fatal_alert_val_2 96.30 88.89 100.00 100.00
u_fatal_alert_val_3 96.30 88.89 100.00 100.00
u_fatal_alert_val_4 96.30 88.89 100.00 100.00
u_fatal_alert_val_5 47.78 33.33 50.00 60.00
u_fatal_alert_val_6 47.78 33.33 50.00 60.00
u_fatal_alert_val_7 47.78 33.33 50.00 60.00
u_fatal_alert_val_8 47.78 33.33 50.00 60.00
u_fatal_alert_val_9 47.78 33.33 50.00 60.00
u_intr_enable_init_status_change 100.00 100.00 100.00 100.00
u_intr_enable_io_status_change 100.00 100.00 100.00 100.00
u_intr_state_init_status_change 100.00 100.00 100.00 100.00
u_intr_state_io_status_change 100.00 100.00 100.00 100.00
u_intr_test_init_status_change 100.00 100.00
u_intr_test_io_status_change 100.00 100.00
u_manual_pad_attr_0_input_disable_0 80.00 80.00
u_manual_pad_attr_0_pull_en_0 80.00 80.00
u_manual_pad_attr_0_pull_select_0 80.00 80.00
u_manual_pad_attr_1_input_disable_1 80.00 80.00
u_manual_pad_attr_1_pull_en_1 80.00 80.00
u_manual_pad_attr_1_pull_select_1 80.00 80.00
u_manual_pad_attr_2_input_disable_2 80.00 80.00
u_manual_pad_attr_2_pull_en_2 80.00 80.00
u_manual_pad_attr_2_pull_select_2 80.00 80.00
u_manual_pad_attr_3_input_disable_3 80.00 80.00
u_manual_pad_attr_3_pull_en_3 80.00 80.00
u_manual_pad_attr_3_pull_select_3 80.00 80.00
u_manual_pad_attr_regwen_0 51.48 44.44 50.00 60.00
u_manual_pad_attr_regwen_1 51.48 44.44 50.00 60.00
u_manual_pad_attr_regwen_2 51.48 44.44 50.00 60.00
u_manual_pad_attr_regwen_3 51.48 44.44 50.00 60.00
u_prim_reg_we_check 100.00 100.00
u_recov_alert_val_0 100.00 100.00 100.00 100.00
u_recov_alert_val_1 100.00 100.00 100.00 100.00
u_recov_alert_val_10 100.00 100.00 100.00 100.00
u_recov_alert_val_2 100.00 100.00 100.00 100.00
u_recov_alert_val_3 100.00 100.00 100.00 100.00
u_recov_alert_val_4 100.00 100.00 100.00 100.00
u_recov_alert_val_5 100.00 100.00 100.00 100.00
u_recov_alert_val_6 100.00 100.00 100.00 100.00
u_recov_alert_val_7 100.00 100.00 100.00 100.00
u_recov_alert_val_8 100.00 100.00 100.00 100.00
u_recov_alert_val_9 100.00 100.00 100.00 100.00
u_reg_if 89.30 94.29 76.54 86.36 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_status_ast_init_done 62.59 77.78 50.00 60.00
u_status_io_pok 62.59 77.78 50.00 60.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sensor_ctrl_reg_top
Line No.TotalCoveredPercent
TOTAL296296100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN43511100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN82311100.00
CONT_ASSIGN85511100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN91911100.00
CONT_ASSIGN95111100.00
CONT_ASSIGN98311100.00
CONT_ASSIGN101511100.00
CONT_ASSIGN104711100.00
CONT_ASSIGN107911100.00
CONT_ASSIGN111111100.00
CONT_ASSIGN114311100.00
CONT_ASSIGN117511100.00
CONT_ASSIGN227711100.00
CONT_ASSIGN228011100.00
CONT_ASSIGN229511100.00
CONT_ASSIGN231111100.00
CONT_ASSIGN232711100.00
CONT_ASSIGN233411100.00
CONT_ASSIGN233711100.00
CONT_ASSIGN235211100.00
CONT_ASSIGN236811100.00
CONT_ASSIGN238411100.00
CONT_ASSIGN239111100.00
CONT_ASSIGN239411100.00
CONT_ASSIGN240911100.00
CONT_ASSIGN242511100.00
CONT_ASSIGN244111100.00
CONT_ASSIGN244811100.00
CONT_ASSIGN245111100.00
CONT_ASSIGN246611100.00
CONT_ASSIGN248211100.00
CONT_ASSIGN249811100.00
ALWAYS25043030100.00
CONT_ASSIGN253611100.00
ALWAYS254011100.00
CONT_ASSIGN257311100.00
CONT_ASSIGN257511100.00
CONT_ASSIGN257711100.00
CONT_ASSIGN257811100.00
CONT_ASSIGN258011100.00
CONT_ASSIGN258211100.00
CONT_ASSIGN258311100.00
CONT_ASSIGN258511100.00
CONT_ASSIGN258711100.00
CONT_ASSIGN258811100.00
CONT_ASSIGN259011100.00
CONT_ASSIGN259211100.00
CONT_ASSIGN259311100.00
CONT_ASSIGN259511100.00
CONT_ASSIGN259611100.00
CONT_ASSIGN259811100.00
CONT_ASSIGN260011100.00
CONT_ASSIGN260211100.00
CONT_ASSIGN260411100.00
CONT_ASSIGN260611100.00
CONT_ASSIGN260811100.00
CONT_ASSIGN261011100.00
CONT_ASSIGN261211100.00
CONT_ASSIGN261411100.00
CONT_ASSIGN261611100.00
CONT_ASSIGN261811100.00
CONT_ASSIGN261911100.00
CONT_ASSIGN262111100.00
CONT_ASSIGN262211100.00
CONT_ASSIGN262411100.00
CONT_ASSIGN262511100.00
CONT_ASSIGN262711100.00
CONT_ASSIGN262811100.00
CONT_ASSIGN263011100.00
CONT_ASSIGN263111100.00
CONT_ASSIGN263311100.00
CONT_ASSIGN263411100.00
CONT_ASSIGN263611100.00
CONT_ASSIGN263711100.00
CONT_ASSIGN263911100.00
CONT_ASSIGN264011100.00
CONT_ASSIGN264211100.00
CONT_ASSIGN264311100.00
CONT_ASSIGN264511100.00
CONT_ASSIGN264611100.00
CONT_ASSIGN264811100.00
CONT_ASSIGN264911100.00
CONT_ASSIGN265111100.00
CONT_ASSIGN265211100.00
CONT_ASSIGN265411100.00
CONT_ASSIGN265611100.00
CONT_ASSIGN265811100.00
CONT_ASSIGN266011100.00
CONT_ASSIGN266211100.00
CONT_ASSIGN266411100.00
CONT_ASSIGN266611100.00
CONT_ASSIGN266811100.00
CONT_ASSIGN267011100.00
CONT_ASSIGN267211100.00
CONT_ASSIGN267411100.00
CONT_ASSIGN267511100.00
CONT_ASSIGN267711100.00
CONT_ASSIGN267911100.00
CONT_ASSIGN268111100.00
CONT_ASSIGN268311100.00
CONT_ASSIGN268511100.00
CONT_ASSIGN268711100.00
CONT_ASSIGN268911100.00
CONT_ASSIGN269111100.00
CONT_ASSIGN269311100.00
CONT_ASSIGN269511100.00
CONT_ASSIGN269711100.00
CONT_ASSIGN269811100.00
CONT_ASSIGN270011100.00
CONT_ASSIGN270111100.00
CONT_ASSIGN270311100.00
CONT_ASSIGN270411100.00
CONT_ASSIGN270611100.00
CONT_ASSIGN270711100.00
CONT_ASSIGN270911100.00
CONT_ASSIGN271011100.00
CONT_ASSIGN271111100.00
CONT_ASSIGN271311100.00
CONT_ASSIGN271511100.00
CONT_ASSIGN271711100.00
CONT_ASSIGN271811100.00
CONT_ASSIGN271911100.00
CONT_ASSIGN272111100.00
CONT_ASSIGN272311100.00
CONT_ASSIGN272511100.00
CONT_ASSIGN272611100.00
CONT_ASSIGN272711100.00
CONT_ASSIGN272911100.00
CONT_ASSIGN273111100.00
CONT_ASSIGN273311100.00
CONT_ASSIGN273411100.00
CONT_ASSIGN273511100.00
CONT_ASSIGN273711100.00
CONT_ASSIGN273911100.00
CONT_ASSIGN274111100.00
ALWAYS27453030100.00
ALWAYS27798585100.00
CONT_ASSIGN296200
CONT_ASSIGN297011100.00
CONT_ASSIGN297111100.00

Click here to see the source line report.

Cond Coverage for Module : sensor_ctrl_reg_top
TotalCoveredPercent
Conditions36925769.65
Logical36925769.65
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT73,T172,T160

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT375,T376,T377
10Not Covered

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT375,T376,T377
010Not Covered
100CoveredT375,T376,T377

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

 LINE       823
 EXPRESSION (alert_en_0_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T70,T161

 LINE       855
 EXPRESSION (alert_en_1_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T162,T70

 LINE       887
 EXPRESSION (alert_en_2_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T70,T161

 LINE       919
 EXPRESSION (alert_en_3_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T70,T161

 LINE       951
 EXPRESSION (alert_en_4_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T162,T70

 LINE       983
 EXPRESSION (alert_en_5_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T70,T161

 LINE       1015
 EXPRESSION (alert_en_6_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T70,T161

 LINE       1047
 EXPRESSION (alert_en_7_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T70,T161

 LINE       1079
 EXPRESSION (alert_en_8_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T70,T161

 LINE       1111
 EXPRESSION (alert_en_9_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T70,T161

 LINE       1143
 EXPRESSION (alert_en_10_we & cfg_regwen_qs)
             -------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT160,T70,T161

 LINE       1175
 EXPRESSION (fatal_alert_en_we & cfg_regwen_qs)
             --------1--------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT162,T139,T54

 LINE       2280
 EXPRESSION (manual_pad_attr_0_we & manual_pad_attr_regwen_0_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T24,T25

 LINE       2337
 EXPRESSION (manual_pad_attr_1_we & manual_pad_attr_regwen_1_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T24,T25

 LINE       2394
 EXPRESSION (manual_pad_attr_2_we & manual_pad_attr_regwen_2_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T24,T25

 LINE       2451
 EXPRESSION (manual_pad_attr_3_we & manual_pad_attr_regwen_3_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T24,T25

 LINE       2505
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2506
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2507
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2508
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2509
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_CFG_REGWEN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2510
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TRIG_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2511
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_0_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2512
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_1_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2513
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_2_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2514
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_3_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2515
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_4_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2516
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_5_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2517
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_6_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2518
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_7_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2519
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_8_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2520
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_9_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2521
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_10_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2522
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_EN_OFFSET)
            ----------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2523
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_RECOV_ALERT_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2524
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2525
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2526
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_0_OFFSET)
            ---------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2527
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_1_OFFSET)
            ---------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2528
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_2_OFFSET)
            ---------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2529
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_3_OFFSET)
            ---------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2530
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_0_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2531
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_1_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2532
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_2_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2533
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_3_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2536
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2536
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT73,T172,T160
10CoveredT1,T2,T3

 LINE       2540
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT73,T172,T160
11Not Covered

 LINE       2540
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T3
29 (addr_hit[28] & ((|(4'...Not Covered
28 (addr_hit[27] & ((|(4'...Not Covered
27 (addr_hit[26] & ((|(4'...Not Covered
26 (addr_hit[25] & ((|(4'...Not Covered
25 (addr_hit[24] & ((|(4'...Not Covered
24 (addr_hit[23] & ((|(4'...Not Covered
23 (addr_hit[22] & ((|(4'...Not Covered
22 (addr_hit[21] & ((|(4'...Not Covered
21 (addr_hit[20] & ((|(4'...Not Covered
20 (addr_hit[19] & ((|(4'...CoveredT23,T24,T25
19 (addr_hit[18] & ((|(4'...CoveredT23,T24,T25
18 (addr_hit[17] & ((|(4'...CoveredT23,T24,T25
17 (addr_hit[16] & ((|(4'...Not Covered
16 (addr_hit[15] & ((|(4'...Not Covered
15 (addr_hit[14] & ((|(4'...Not Covered
14 (addr_hit[13] & ((|(4'...Not Covered
13 (addr_hit[12] & ((|(4'...Not Covered
12 (addr_hit[11] & ((|(4'...Not Covered
11 (addr_hit[10] & ((|(4'...Not Covered
10 (addr_hit[9] & ((|(4'b...Not Covered
9 (addr_hit[8] & ((|(4'b...Not Covered
8 (addr_hit[7] & ((|(4'b...Not Covered
7 (addr_hit[6] & ((|(4'b...Not Covered
6 (addr_hit[5] & ((|(4'b...CoveredT23,T24,T25
5 (addr_hit[4] & ((|(4'b...Not Covered
4 (addr_hit[3] & ((|(4'b...Not Covered
3 (addr_hit[2] & ((|(4'b...Not Covered
2 (addr_hit[1] & ((|(4'b...Not Covered
1 (addr_hit[0] & ((|(4'b...CoveredT1,T2,T3

 LINE       2540
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2540
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT23,T24,T25

 LINE       2540
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT23,T24,T25

 LINE       2540
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT23,T24,T25

 LINE       2540
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT23,T24,T25

 LINE       2540
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2573
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT172,T120,T335

 LINE       2578
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT172,T120,T335

 LINE       2583
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT120,T183,T184

 LINE       2588
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT172,T160,T120
101CoveredT1,T2,T3
110Not Covered
111CoveredT73,T74,T75

 LINE       2593
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2596
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T162,T70

 LINE       2619
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T70,T161

 LINE       2622
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T162,T70

 LINE       2625
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T70,T161

 LINE       2628
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T70,T161

 LINE       2631
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T162,T70

 LINE       2634
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T70,T161

 LINE       2637
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T70,T161

 LINE       2640
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T70,T161

 LINE       2643
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T70,T161

 LINE       2646
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T70,T161

 LINE       2649
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T70,T161

 LINE       2652
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT162,T139,T54

 LINE       2675
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT160,T162,T70

 LINE       2698
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2701
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2704
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2707
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2710
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2711
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT23,T24,T25

 LINE       2718
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2719
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT23,T24,T25

 LINE       2726
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2727
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT23,T24,T25

 LINE       2734
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2735
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT73,T172,T160
101CoveredT1,T2,T3
110Not Covered
111CoveredT23,T24,T25

Branch Coverage for Module : sensor_ctrl_reg_top
Line No.TotalCoveredPercent
Branches 35 35 100.00
TERNARY 2536 2 2 100.00
IF 68 3 3 100.00
CASE 2780 30 30 100.00


2536 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


68 if (!rst_ni) begin -1- 69 err_q <= '0; ==> 70 end else if (intg_err || reg_we_err) begin -2- 71 err_q <= 1'b1; ==> 72 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T375,T376,T377
0 0 Covered T1,T2,T3


2780 unique case (1'b1) -1- 2781 addr_hit[0]: begin 2782 reg_rdata_next[0] = intr_state_io_status_change_qs; ==> 2783 reg_rdata_next[1] = intr_state_init_status_change_qs; 2784 end 2785 2786 addr_hit[1]: begin 2787 reg_rdata_next[0] = intr_enable_io_status_change_qs; ==> 2788 reg_rdata_next[1] = intr_enable_init_status_change_qs; 2789 end 2790 2791 addr_hit[2]: begin 2792 reg_rdata_next[0] = '0; ==> 2793 reg_rdata_next[1] = '0; 2794 end 2795 2796 addr_hit[3]: begin 2797 reg_rdata_next[0] = '0; ==> 2798 reg_rdata_next[1] = '0; 2799 end 2800 2801 addr_hit[4]: begin 2802 reg_rdata_next[0] = cfg_regwen_qs; ==> 2803 end 2804 2805 addr_hit[5]: begin 2806 reg_rdata_next[0] = alert_trig_val_0_qs; ==> 2807 reg_rdata_next[1] = alert_trig_val_1_qs; 2808 reg_rdata_next[2] = alert_trig_val_2_qs; 2809 reg_rdata_next[3] = alert_trig_val_3_qs; 2810 reg_rdata_next[4] = alert_trig_val_4_qs; 2811 reg_rdata_next[5] = alert_trig_val_5_qs; 2812 reg_rdata_next[6] = alert_trig_val_6_qs; 2813 reg_rdata_next[7] = alert_trig_val_7_qs; 2814 reg_rdata_next[8] = alert_trig_val_8_qs; 2815 reg_rdata_next[9] = alert_trig_val_9_qs; 2816 reg_rdata_next[10] = alert_trig_val_10_qs; 2817 end 2818 2819 addr_hit[6]: begin 2820 reg_rdata_next[3:0] = alert_en_0_qs; ==> 2821 end 2822 2823 addr_hit[7]: begin 2824 reg_rdata_next[3:0] = alert_en_1_qs; ==> 2825 end 2826 2827 addr_hit[8]: begin 2828 reg_rdata_next[3:0] = alert_en_2_qs; ==> 2829 end 2830 2831 addr_hit[9]: begin 2832 reg_rdata_next[3:0] = alert_en_3_qs; ==> 2833 end 2834 2835 addr_hit[10]: begin 2836 reg_rdata_next[3:0] = alert_en_4_qs; ==> 2837 end 2838 2839 addr_hit[11]: begin 2840 reg_rdata_next[3:0] = alert_en_5_qs; ==> 2841 end 2842 2843 addr_hit[12]: begin 2844 reg_rdata_next[3:0] = alert_en_6_qs; ==> 2845 end 2846 2847 addr_hit[13]: begin 2848 reg_rdata_next[3:0] = alert_en_7_qs; ==> 2849 end 2850 2851 addr_hit[14]: begin 2852 reg_rdata_next[3:0] = alert_en_8_qs; ==> 2853 end 2854 2855 addr_hit[15]: begin 2856 reg_rdata_next[3:0] = alert_en_9_qs; ==> 2857 end 2858 2859 addr_hit[16]: begin 2860 reg_rdata_next[3:0] = alert_en_10_qs; ==> 2861 end 2862 2863 addr_hit[17]: begin 2864 reg_rdata_next[0] = fatal_alert_en_val_0_qs; ==> 2865 reg_rdata_next[1] = fatal_alert_en_val_1_qs; 2866 reg_rdata_next[2] = fatal_alert_en_val_2_qs; 2867 reg_rdata_next[3] = fatal_alert_en_val_3_qs; 2868 reg_rdata_next[4] = fatal_alert_en_val_4_qs; 2869 reg_rdata_next[5] = fatal_alert_en_val_5_qs; 2870 reg_rdata_next[6] = fatal_alert_en_val_6_qs; 2871 reg_rdata_next[7] = fatal_alert_en_val_7_qs; 2872 reg_rdata_next[8] = fatal_alert_en_val_8_qs; 2873 reg_rdata_next[9] = fatal_alert_en_val_9_qs; 2874 reg_rdata_next[10] = fatal_alert_en_val_10_qs; 2875 end 2876 2877 addr_hit[18]: begin 2878 reg_rdata_next[0] = recov_alert_val_0_qs; ==> 2879 reg_rdata_next[1] = recov_alert_val_1_qs; 2880 reg_rdata_next[2] = recov_alert_val_2_qs; 2881 reg_rdata_next[3] = recov_alert_val_3_qs; 2882 reg_rdata_next[4] = recov_alert_val_4_qs; 2883 reg_rdata_next[5] = recov_alert_val_5_qs; 2884 reg_rdata_next[6] = recov_alert_val_6_qs; 2885 reg_rdata_next[7] = recov_alert_val_7_qs; 2886 reg_rdata_next[8] = recov_alert_val_8_qs; 2887 reg_rdata_next[9] = recov_alert_val_9_qs; 2888 reg_rdata_next[10] = recov_alert_val_10_qs; 2889 end 2890 2891 addr_hit[19]: begin 2892 reg_rdata_next[0] = fatal_alert_val_0_qs; ==> 2893 reg_rdata_next[1] = fatal_alert_val_1_qs; 2894 reg_rdata_next[2] = fatal_alert_val_2_qs; 2895 reg_rdata_next[3] = fatal_alert_val_3_qs; 2896 reg_rdata_next[4] = fatal_alert_val_4_qs; 2897 reg_rdata_next[5] = fatal_alert_val_5_qs; 2898 reg_rdata_next[6] = fatal_alert_val_6_qs; 2899 reg_rdata_next[7] = fatal_alert_val_7_qs; 2900 reg_rdata_next[8] = fatal_alert_val_8_qs; 2901 reg_rdata_next[9] = fatal_alert_val_9_qs; 2902 reg_rdata_next[10] = fatal_alert_val_10_qs; 2903 reg_rdata_next[11] = fatal_alert_val_11_qs; 2904 end 2905 2906 addr_hit[20]: begin 2907 reg_rdata_next[0] = status_ast_init_done_qs; ==> 2908 reg_rdata_next[2:1] = status_io_pok_qs; 2909 end 2910 2911 addr_hit[21]: begin 2912 reg_rdata_next[0] = manual_pad_attr_regwen_0_qs; ==> 2913 end 2914 2915 addr_hit[22]: begin 2916 reg_rdata_next[0] = manual_pad_attr_regwen_1_qs; ==> 2917 end 2918 2919 addr_hit[23]: begin 2920 reg_rdata_next[0] = manual_pad_attr_regwen_2_qs; ==> 2921 end 2922 2923 addr_hit[24]: begin 2924 reg_rdata_next[0] = manual_pad_attr_regwen_3_qs; ==> 2925 end 2926 2927 addr_hit[25]: begin 2928 reg_rdata_next[2] = manual_pad_attr_0_pull_en_0_qs; ==> 2929 reg_rdata_next[3] = manual_pad_attr_0_pull_select_0_qs; 2930 reg_rdata_next[7] = manual_pad_attr_0_input_disable_0_qs; 2931 end 2932 2933 addr_hit[26]: begin 2934 reg_rdata_next[2] = manual_pad_attr_1_pull_en_1_qs; ==> 2935 reg_rdata_next[3] = manual_pad_attr_1_pull_select_1_qs; 2936 reg_rdata_next[7] = manual_pad_attr_1_input_disable_1_qs; 2937 end 2938 2939 addr_hit[27]: begin 2940 reg_rdata_next[2] = manual_pad_attr_2_pull_en_2_qs; ==> 2941 reg_rdata_next[3] = manual_pad_attr_2_pull_select_2_qs; 2942 reg_rdata_next[7] = manual_pad_attr_2_input_disable_2_qs; 2943 end 2944 2945 addr_hit[28]: begin 2946 reg_rdata_next[2] = manual_pad_attr_3_pull_en_3_qs; ==> 2947 reg_rdata_next[3] = manual_pad_attr_3_pull_select_3_qs; 2948 reg_rdata_next[7] = manual_pad_attr_3_input_disable_3_qs; 2949 end 2950 2951 default: begin 2952 reg_rdata_next = '1; ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : sensor_ctrl_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
en2addrHit 124273205 5395 0 0
reAfterRv 124273205 5395 0 0
rePulse 124273205 3905 0 0
wePulse 124273205 1490 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 124273205 5395 0 0
T1 10520 1 0 0
T2 22036 1 0 0
T3 14065 1 0 0
T4 22996 1 0 0
T5 25970 1 0 0
T6 25819 1 0 0
T7 19427 1 0 0
T8 25844 1 0 0
T10 20406 1 0 0
T35 23415 1 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 124273205 5395 0 0
T1 10520 1 0 0
T2 22036 1 0 0
T3 14065 1 0 0
T4 22996 1 0 0
T5 25970 1 0 0
T6 25819 1 0 0
T7 19427 1 0 0
T8 25844 1 0 0
T10 20406 1 0 0
T35 23415 1 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 124273205 3905 0 0
T1 10520 1 0 0
T2 22036 1 0 0
T3 14065 1 0 0
T4 22996 1 0 0
T5 25970 1 0 0
T6 25819 1 0 0
T7 19427 1 0 0
T8 25844 1 0 0
T10 20406 1 0 0
T35 23415 1 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 124273205 1490 0 0
T18 44412 0 0 0
T36 114794 0 0 0
T68 74872 0 0 0
T70 0 14 0 0
T72 0 80 0 0
T73 26105 2 0 0
T120 0 6 0 0
T139 0 36 0 0
T152 45007 0 0 0
T160 0 55 0 0
T161 0 28 0 0
T162 0 26 0 0
T172 0 12 0 0
T189 96518 0 0 0
T198 104307 0 0 0
T199 98800 0 0 0
T275 55879 0 0 0
T378 0 1 0 0
T379 25652 0 0 0