Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T43,T33,T38	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T37,*T59	Yes	T87,T37,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T59,T97	Yes	T37,T59,T97	INPUT
tl_i.a_valid	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	INPUT
tl_o.a_ready	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
tl_o.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T56,*T57,*T97	Yes	T56,T57,T97	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T127,*T64,*T129	Yes	T127,T64,T129	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T73,T333,T99	Yes	T73,T333,T99	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T73,T333,T99	Yes	T73,T333,T99	OUTPUT
cio_rx_i	Yes	Yes	T8,T43,T127	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
intr_tx_empty_o	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
intr_rx_watermark_o	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
intr_tx_done_o	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
intr_rx_overflow_o	Yes	Yes	T127,T64,T129	Yes	T127,T64,T129	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T43,T33,T38	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T127,T246,T128	Yes	T127,T246,T128	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T127,T246,T128	Yes	T127,T246,T128	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T37,*T59	Yes	T87,T37,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T59,T97	Yes	T37,T59,T97	INPUT
tl_i.a_valid	Yes	Yes	T127,T73,T246	Yes	T127,T73,T246	INPUT
tl_o.a_ready	Yes	Yes	T127,T73,T128	Yes	T127,T73,T128	OUTPUT
tl_o.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T127,T128,T323	Yes	T127,T128,T323	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T127,T128,T186	Yes	T127,T73,T128	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T127,T128,T186	Yes	T127,T73,T128	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T96,T98	Yes	T94,T96,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T56,*T57,*T97	Yes	T56,T57,T97	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T94,T95,T98	Yes	T94,T98,T158	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T127,*T128,*T323	Yes	T127,T128,T323	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T127,T73,T128	Yes	T127,T73,T128	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T73,T333,T99	Yes	T73,T333,T99	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T73,T333,T99	Yes	T73,T333,T99	OUTPUT
cio_rx_i	Yes	Yes	T8,T43,T127	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T127,T128,T55	Yes	T127,T128,T55	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T127,T128,T323	Yes	T127,T128,T323	OUTPUT
intr_tx_empty_o	Yes	Yes	T127,T128,T323	Yes	T127,T128,T323	OUTPUT
intr_rx_watermark_o	Yes	Yes	T127,T128,T323	Yes	T127,T128,T323	OUTPUT
intr_tx_done_o	Yes	Yes	T127,T128,T323	Yes	T127,T128,T323	OUTPUT
intr_rx_overflow_o	Yes	Yes	T127,T128,T323	Yes	T127,T128,T323	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T43,T33,T38	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T129,T323,T51	Yes	T129,T323,T51	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T129,T323,T51	Yes	T129,T323,T51	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T37,*T59	Yes	T87,T37,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T59,T97	Yes	T37,T59,T97	INPUT
tl_i.a_valid	Yes	Yes	T129,T73,T186	Yes	T129,T73,T186	INPUT
tl_o.a_ready	Yes	Yes	T129,T73,T186	Yes	T129,T73,T186	OUTPUT
tl_o.d_error	Yes	Yes	T95,T96,T98	Yes	T95,T96,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T129,T323,T51	Yes	T129,T323,T51	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T129,T186,T323	Yes	T129,T73,T186	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T129,T186,T323	Yes	T129,T73,T186	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T95,T96,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T97,*T96,*T98	Yes	T97,T94,T95	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T129,*T323,*T51	Yes	T129,T323,T51	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T129,T73,T186	Yes	T129,T73,T186	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T73,T99,T186	Yes	T73,T99,T186	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T73,T99,T186	Yes	T73,T99,T186	OUTPUT
cio_rx_i	Yes	Yes	T129,T130,T131	Yes	T8,T10,T129	INPUT
cio_tx_o	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T129,T323,T130	Yes	T129,T323,T130	OUTPUT
intr_tx_empty_o	Yes	Yes	T129,T323,T130	Yes	T129,T323,T130	OUTPUT
intr_rx_watermark_o	Yes	Yes	T129,T323,T130	Yes	T129,T323,T130	OUTPUT
intr_tx_done_o	Yes	Yes	T129,T323,T130	Yes	T129,T323,T130	OUTPUT
intr_rx_overflow_o	Yes	Yes	T129,T323,T130	Yes	T129,T323,T130	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T43,T33,T38	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T64,T65,T323	Yes	T64,T65,T323	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T64,T65,T323	Yes	T64,T65,T323	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T37,*T59	Yes	T87,T37,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T59,T97	Yes	T37,T59,T97	INPUT
tl_i.a_valid	Yes	Yes	T64,T65,T73	Yes	T64,T65,T73	INPUT
tl_o.a_ready	Yes	Yes	T64,T65,T73	Yes	T64,T65,T73	OUTPUT
tl_o.d_error	Yes	Yes	T95,T98,T158	Yes	T95,T98,T158	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T64,T65,T323	Yes	T64,T65,T323	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T64,T65,T186	Yes	T64,T65,T73	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T64,T65,T186	Yes	T64,T65,T73	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T97,*T95,*T98	Yes	T97,T94,T95	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T94,T95,T98	Yes	T94,T95,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T64,*T65,*T323	Yes	T64,T65,T323	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T64,T65,T73	Yes	T64,T65,T73	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T73,T99,T186	Yes	T73,T99,T186	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T73,T99,T186	Yes	T73,T99,T186	OUTPUT
cio_rx_i	Yes	Yes	T64,T65,T132	Yes	T64,T65,T132	INPUT
cio_tx_o	Yes	Yes	T64,T65,T132	Yes	T64,T65,T132	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T64,T65,T323	Yes	T64,T65,T323	OUTPUT
intr_tx_empty_o	Yes	Yes	T64,T65,T323	Yes	T64,T65,T323	OUTPUT
intr_rx_watermark_o	Yes	Yes	T64,T65,T323	Yes	T64,T65,T323	OUTPUT
intr_tx_done_o	Yes	Yes	T64,T65,T323	Yes	T64,T65,T323	OUTPUT
intr_rx_overflow_o	Yes	Yes	T64,T65,T323	Yes	T64,T65,T323	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T43,T33,T38	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T29,T66,T323	Yes	T29,T66,T323	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T29,T66,T323	Yes	T29,T66,T323	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T37,*T59	Yes	T87,T37,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T59,T97	Yes	T37,T59,T97	INPUT
tl_i.a_valid	Yes	Yes	T29,T66,T73	Yes	T29,T66,T73	INPUT
tl_o.a_ready	Yes	Yes	T29,T66,T73	Yes	T29,T66,T73	OUTPUT
tl_o.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T29,T66,T323	Yes	T29,T66,T323	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T29,T66,T186	Yes	T29,T66,T73	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T29,T66,T186	Yes	T29,T66,T73	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T96,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T97,*T96,*T98	Yes	T97,T95,T96	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T29,*T66,*T323	Yes	T29,T66,T323	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T29,T66,T73	Yes	T29,T66,T73	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T73,T99,T186	Yes	T73,T99,T186	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T73,T99,T186	Yes	T73,T99,T186	OUTPUT
cio_rx_i	Yes	Yes	T29,T66,T133	Yes	T29,T66,T133	INPUT
cio_tx_o	Yes	Yes	T29,T66,T133	Yes	T29,T66,T133	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T29,T66,T323	Yes	T29,T66,T323	OUTPUT
intr_tx_empty_o	Yes	Yes	T29,T66,T323	Yes	T29,T66,T323	OUTPUT
intr_rx_watermark_o	Yes	Yes	T29,T66,T323	Yes	T29,T66,T323	OUTPUT
intr_tx_done_o	Yes	Yes	T29,T66,T323	Yes	T29,T66,T323	OUTPUT
intr_rx_overflow_o	Yes	Yes	T29,T66,T323	Yes	T29,T66,T323	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T327,T328	Yes	T323,T327,T328	OUTPUT

*Tests covering at least one bit in the range