Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_por_aon_n_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T8 T10 T13 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T11,T12
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T11
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T11,T12

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23030	22510	0	0
selKnown1	128826	127440	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23030	22510	0	0
T11	169	168	0	0
T12	19	18	0	0
T23	3	16	0	0
T24	7	6	0	0
T25	4	3	0	0
T30	4	3	0	0
T33	2	1	0	0
T34	1	0	0	0
T38	2	1	0	0
T39	2	1	0	0
T58	1	0	0	0
T80	1	0	0	0
T88	0	1	0	0
T189	3	2	0	0
T191	0	15	0	0
T192	2	1	0	0
T213	6	5	0	0
T214	0	2	0	0
T215	4	3	0	0
T216	4	3	0	0
T217	3	2	0	0
T218	6	5	0	0
T219	7	6	0	0
T220	7	6	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	128826	127440	0	0
T13	1	0	0	0
T23	16	14	0	0
T24	24	22	0	0
T25	14	12	0	0
T30	1	0	0	0
T33	2	1	0	0
T34	1	0	0	0
T38	2	1	0	0
T39	0	1	0	0
T43	2	1	0	0
T44	0	1	0	0
T51	576	575	0	0
T58	1	0	0	0
T80	1	0	0	0
T81	0	1	0	0
T127	1	0	0	0
T181	1	0	0	0
T182	0	1	0	0
T192	0	1	0	0
T200	0	1	0	0
T215	21	43	0	0
T216	4	11	0	0
T217	16	36	0	0
T218	10	14	0	0
T219	10	9	0	0
T220	19	18	0	0
T221	0	1	0	0
T222	24	23	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T33
0	1	Covered	T8,T30,T33
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T30,T33
1	1	Covered	T8,T30,T33

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	780	648	0	0
selKnown1	1731	723	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	780	648	0	0
T30	4	3	0	0
T33	2	1	0	0
T34	1	0	0	0
T38	2	1	0	0
T39	2	1	0	0
T58	1	0	0	0
T80	1	0	0	0
T88	0	1	0	0
T189	3	2	0	0
T191	0	15	0	0
T192	2	1	0	0
T213	6	5	0	0
T214	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1731	723	0	0
T13	1	0	0	0
T30	1	0	0	0
T33	2	1	0	0
T34	1	0	0	0
T38	2	1	0	0
T39	0	1	0	0
T43	2	1	0	0
T44	0	1	0	0
T58	1	0	0	0
T80	1	0	0	0
T81	0	1	0	0
T127	1	0	0	0
T181	1	0	0	0
T182	0	1	0	0
T192	0	1	0	0
T200	0	1	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T11 T12 T51 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T51,T28
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T51
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T51,T28

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	3790	3769	0	0
selKnown1	1887	1868	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	3790	3769	0	0
T11	169	168	0	0
T12	19	18	0	0
T22	1	0	0	0
T23	0	14	0	0
T28	1	0	0	0
T51	1026	1025	0	0
T125	1026	1025	0	0
T126	0	1025	0	0
T223	166	165	0	0
T224	19	18	0	0
T225	189	188	0	0
T226	19	18	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1887	1868	0	0
T23	8	7	0	0
T24	13	12	0	0
T25	9	8	0	0
T51	576	575	0	0
T125	576	575	0	0
T126	576	575	0	0
T215	0	23	0	0
T216	0	8	0	0
T217	0	21	0	0
T218	0	5	0	0
T223	1	0	0	0
T224	1	0	0	0
T225	1	0	0	0
T226	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T8 T51 T28 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T22,T23
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T51,T28
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T28,T22,T23

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	48	36	0	0
selKnown1	134	118	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	48	36	0	0
T23	3	2	0	0
T24	7	6	0	0
T25	4	3	0	0
T215	4	3	0	0
T216	4	3	0	0
T217	3	2	0	0
T218	6	5	0	0
T219	7	6	0	0
T220	7	6	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	134	118	0	0
T23	8	7	0	0
T24	11	10	0	0
T25	5	4	0	0
T215	21	20	0	0
T216	4	3	0	0
T217	16	15	0	0
T218	10	9	0	0
T219	10	9	0	0
T220	19	18	0	0
T222	24	23	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T10 T11 T12 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T51,T28
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T51,T45
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T51,T28

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	3827	3807	0	0
selKnown1	135	119	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	3827	3807	0	0
T11	181	180	0	0
T12	19	18	0	0
T23	0	15	0	0
T28	1	0	0	0
T51	1025	1024	0	0
T125	1025	1024	0	0
T126	1026	1025	0	0
T223	172	171	0	0
T224	19	18	0	0
T225	205	204	0	0
T226	19	18	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	135	119	0	0
T23	11	10	0	0
T24	7	6	0	0
T25	9	8	0	0
T45	1	0	0	0
T46	1	0	0	0
T51	2	1	0	0
T125	2	1	0	0
T126	2	1	0	0
T215	16	15	0	0
T216	11	10	0	0
T217	0	8	0	0
T218	0	6	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T51 T28 T22 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T22,T23
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T51,T28,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T28,T22,T23

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	58	46	0	0
selKnown1	117	102	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	58	46	0	0
T23	6	5	0	0
T24	9	8	0	0
T25	5	4	0	0
T215	4	3	0	0
T216	9	8	0	0
T217	2	1	0	0
T218	6	5	0	0
T219	4	3	0	0
T220	9	8	0	0
T222	2	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	117	102	0	0
T23	6	5	0	0
T24	5	4	0	0
T25	5	4	0	0
T215	15	14	0	0
T216	12	11	0	0
T217	14	13	0	0
T218	7	6	0	0
T219	10	9	0	0
T220	17	16	0	0
T222	21	20	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T8 T13 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T11,T12
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T51,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T11,T12

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4129	4107	0	0
selKnown1	500	485	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4129	4107	0	0
T11	287	286	0	0
T12	1	0	0	0
T23	0	14	0	0
T24	0	21	0	0
T25	0	9	0	0
T51	1025	1024	0	0
T78	1	0	0	0
T79	1	0	0	0
T125	1025	1024	0	0
T126	0	1024	0	0
T215	0	16	0	0
T223	277	276	0	0
T224	1	0	0	0
T225	346	345	0	0
T226	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	500	485	0	0
T22	1	0	0	0
T23	11	10	0	0
T24	13	12	0	0
T25	8	7	0	0
T51	117	116	0	0
T125	117	116	0	0
T126	116	115	0	0
T215	18	17	0	0
T216	6	5	0	0
T217	28	27	0	0
T218	0	5	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T8 T13 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T51,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T13,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	68	48	0	0
selKnown1	124	109	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	68	48	0	0
T11	3	2	0	0
T23	5	4	0	0
T24	12	11	0	0
T25	0	1	0	0
T51	1	0	0	0
T78	1	0	0	0
T79	1	0	0	0
T125	1	0	0	0
T126	1	0	0	0
T215	0	4	0	0
T216	0	1	0	0
T217	0	3	0	0
T218	0	8	0	0
T223	3	2	0	0
T225	3	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	124	109	0	0
T23	9	8	0	0
T24	11	10	0	0
T25	7	6	0	0
T215	19	18	0	0
T216	3	2	0	0
T217	21	20	0	0
T218	8	7	0	0
T219	13	12	0	0
T220	12	11	0	0
T222	16	15	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T13 T11 T12 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T11,T12
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T11,T12

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4159	4137	0	0
selKnown1	133	122	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4159	4137	0	0
T11	300	299	0	0
T12	1	0	0	0
T23	0	15	0	0
T24	0	21	0	0
T25	0	15	0	0
T51	1025	1024	0	0
T78	1	0	0	0
T79	1	0	0	0
T125	1025	1024	0	0
T126	0	1025	0	0
T215	0	12	0	0
T223	282	281	0	0
T224	1	0	0	0
T225	361	360	0	0
T226	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	133	122	0	0
T23	5	4	0	0
T24	7	6	0	0
T25	7	6	0	0
T215	14	13	0	0
T216	9	8	0	0
T217	19	18	0	0
T218	6	5	0	0
T219	13	12	0	0
T220	30	29	0	0
T222	22	21	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T8 T13 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T51,T28,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T13,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	73	52	0	0
selKnown1	120	105	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	73	52	0	0
T11	3	2	0	0
T22	1	0	0	0
T23	2	1	0	0
T24	0	10	0	0
T25	0	4	0	0
T51	1	0	0	0
T78	1	0	0	0
T79	1	0	0	0
T125	1	0	0	0
T126	1	0	0	0
T215	0	1	0	0
T216	0	7	0	0
T217	0	2	0	0
T218	0	3	0	0
T223	3	2	0	0
T225	3	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	120	105	0	0
T23	10	9	0	0
T24	11	10	0	0
T25	4	3	0	0
T215	11	10	0	0
T216	6	5	0	0
T217	13	12	0	0
T218	2	1	0	0
T219	13	12	0	0
T220	24	23	0	0
T222	21	20	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T8 T10 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T59
0	1	Covered	T10,T51,T45
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T8,T37,T59
1	1	Covered	T10,T51,T45

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1927	1905	0	0
selKnown1	3613	3582	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1905	0	0
T23	15	14	0	0
T24	0	23	0	0
T25	0	8	0	0
T45	1	0	0	0
T46	1	0	0	0
T51	576	575	0	0
T97	1	0	0	0
T125	576	575	0	0
T126	576	575	0	0
T215	0	22	0	0
T216	0	18	0	0
T217	0	11	0	0
T218	0	14	0	0
T227	1	0	0	0
T228	1	0	0	0
T229	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	3613	3582	0	0
T11	134	133	0	0
T12	1	0	0	0
T23	0	13	0	0
T24	0	9	0	0
T25	0	6	0	0
T28	1	0	0	0
T37	1	0	0	0
T45	1	0	0	0
T51	1025	1024	0	0
T59	1	0	0	0
T97	1	0	0	0
T125	0	1024	0	0
T126	0	1024	0	0
T215	0	10	0	0
T223	132	131	0	0
T224	1	0	0	0
T225	0	151	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T8 T10 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T59
0	1	Covered	T10,T51,T45
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T8,T37,T59
1	1	Covered	T10,T51,T45

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1924	1902	0	0
selKnown1	3611	3580	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1924	1902	0	0
T23	14	13	0	0
T24	0	23	0	0
T25	0	8	0	0
T45	1	0	0	0
T46	1	0	0	0
T51	576	575	0	0
T97	1	0	0	0
T125	576	575	0	0
T126	576	575	0	0
T215	0	25	0	0
T216	0	18	0	0
T217	0	12	0	0
T218	0	12	0	0
T227	1	0	0	0
T228	1	0	0	0
T229	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	3611	3580	0	0
T11	134	133	0	0
T12	1	0	0	0
T23	0	12	0	0
T24	0	8	0	0
T25	0	6	0	0
T28	1	0	0	0
T37	1	0	0	0
T45	1	0	0	0
T51	1025	1024	0	0
T59	1	0	0	0
T97	1	0	0	0
T125	0	1024	0	0
T126	0	1024	0	0
T215	0	10	0	0
T223	132	131	0	0
T224	1	0	0	0
T225	0	151	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T8 T10 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T59
0	1	Covered	T8,T10,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T8,T37,T59
1	1	Covered	T8,T10,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	187	158	0	0
selKnown1	3665	3635	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	187	158	0	0
T23	0	8	0	0
T24	0	16	0	0
T25	0	28	0	0
T45	1	0	0	0
T46	1	0	0	0
T51	2	1	0	0
T97	1	0	0	0
T125	2	1	0	0
T126	0	1	0	0
T215	0	10	0	0
T216	0	18	0	0
T217	0	16	0	0
T218	0	2	0	0
T223	1	0	0	0
T224	1	0	0	0
T225	1	0	0	0
T226	1	0	0	0
T227	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	3665	3635	0	0
T11	147	146	0	0
T12	1	0	0	0
T23	0	16	0	0
T24	0	15	0	0
T25	0	6	0	0
T28	1	0	0	0
T37	1	0	0	0
T45	1	0	0	0
T51	1025	1024	0	0
T59	1	0	0	0
T97	1	0	0	0
T125	0	1024	0	0
T126	0	1025	0	0
T215	0	19	0	0
T223	137	136	0	0
T224	1	0	0	0
T225	0	166	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T8 T10 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T59
0	1	Covered	T8,T10,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T8,T37,T59
1	1	Covered	T8,T10,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	184	155	0	0
selKnown1	3664	3634	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	184	155	0	0
T23	0	7	0	0
T24	0	17	0	0
T25	0	26	0	0
T45	1	0	0	0
T46	1	0	0	0
T51	2	1	0	0
T97	1	0	0	0
T125	2	1	0	0
T126	0	1	0	0
T215	0	11	0	0
T216	0	18	0	0
T217	0	16	0	0
T218	0	3	0	0
T223	1	0	0	0
T224	1	0	0	0
T225	1	0	0	0
T226	1	0	0	0
T227	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	3664	3634	0	0
T11	147	146	0	0
T12	1	0	0	0
T23	0	16	0	0
T24	0	15	0	0
T25	0	6	0	0
T28	1	0	0	0
T37	1	0	0	0
T45	1	0	0	0
T51	1025	1024	0	0
T59	1	0	0	0
T97	1	0	0	0
T125	0	1024	0	0
T126	0	1025	0	0
T215	0	18	0	0
T223	137	136	0	0
T224	1	0	0	0
T225	0	166	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T2 T8 T14 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T37
0	1	Covered	T2,T8,T51
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T11,T51
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T13,T37
1	1	Covered	T2,T8,T51

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	574	551	0	0
selKnown1	27343	27309	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	574	551	0	0
T22	1	0	0	0
T23	10	9	0	0
T24	0	17	0	0
T25	0	28	0	0
T28	1	0	0	0
T51	117	116	0	0
T97	1	0	0	0
T125	117	116	0	0
T126	116	115	0	0
T215	0	23	0	0
T216	0	10	0	0
T217	0	37	0	0
T218	0	15	0	0
T227	1	0	0	0
T228	1	0	0	0
T229	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27343	27309	0	0
T11	321	320	0	0
T12	18	17	0	0
T13	2	1	0	0
T14	20	19	0	0
T28	2	1	0	0
T49	20	19	0	0
T51	1025	1024	0	0
T78	2	1	0	0
T223	309	308	0	0
T224	18	17	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T2 T8 T14 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T37
0	1	Covered	T2,T8,T51
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T11,T51
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T13,T37
1	1	Covered	T2,T8,T51

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	574	551	0	0
selKnown1	27343	27309	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	574	551	0	0
T22	1	0	0	0
T23	11	10	0	0
T24	0	15	0	0
T25	0	26	0	0
T28	1	0	0	0
T51	117	116	0	0
T97	1	0	0	0
T125	117	116	0	0
T126	116	115	0	0
T215	0	23	0	0
T216	0	10	0	0
T217	0	38	0	0
T218	0	15	0	0
T227	1	0	0	0
T228	1	0	0	0
T229	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27343	27309	0	0
T11	321	320	0	0
T12	18	17	0	0
T13	2	1	0	0
T14	20	19	0	0
T28	2	1	0	0
T49	20	19	0	0
T51	1025	1024	0	0
T78	2	1	0	0
T223	309	308	0	0
T224	18	17	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T2 T8 T10 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T15
0	1	Covered	T8,T10,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T11,T51
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T8,T31,T15
1	1	Covered	T8,T10,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	365	320	0	0
selKnown1	27353	27320	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	365	320	0	0
T15	8	7	0	0
T16	2	1	0	0
T17	1	0	0	0
T31	2	1	0	0
T37	1	0	0	0
T45	1	0	0	0
T51	2	1	0	0
T59	1	0	0	0
T67	31	30	0	0
T125	0	1	0	0
T223	1	0	0	0
T230	0	1	0	0
T231	0	7	0	0
T232	0	32	0	0
T233	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27353	27320	0	0
T11	333	332	0	0
T12	18	17	0	0
T13	2	1	0	0
T14	20	19	0	0
T28	2	1	0	0
T49	20	19	0	0
T51	1024	1023	0	0
T78	2	1	0	0
T223	315	314	0	0
T224	18	17	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T2 T8 T10 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T15
0	1	Covered	T8,T10,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T11,T51
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T8,T31,T15
1	1	Covered	T8,T10,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	363	318	0	0
selKnown1	27353	27320	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	363	318	0	0
T15	8	7	0	0
T16	2	1	0	0
T17	1	0	0	0
T31	2	1	0	0
T37	1	0	0	0
T45	1	0	0	0
T51	2	1	0	0
T59	1	0	0	0
T67	31	30	0	0
T125	0	1	0	0
T223	1	0	0	0
T230	0	1	0	0
T231	0	7	0	0
T232	0	32	0	0
T233	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27353	27320	0	0
T11	333	332	0	0
T12	18	17	0	0
T13	2	1	0	0
T14	20	19	0	0
T28	2	1	0	0
T49	20	19	0	0
T51	1024	1023	0	0
T78	2	1	0	0
T223	315	314	0	0
T224	18	17	0	0