Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_por_aon_n_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T8 T10 T13 

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T11,T12
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T10,T11
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT13,T11,T12

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23030 22510 0 0
selKnown1 128826 127440 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23030 22510 0 0
T11 169 168 0 0
T12 19 18 0 0
T23 3 16 0 0
T24 7 6 0 0
T25 4 3 0 0
T30 4 3 0 0
T33 2 1 0 0
T34 1 0 0 0
T38 2 1 0 0
T39 2 1 0 0
T58 1 0 0 0
T80 1 0 0 0
T88 0 1 0 0
T189 3 2 0 0
T191 0 15 0 0
T192 2 1 0 0
T213 6 5 0 0
T214 0 2 0 0
T215 4 3 0 0
T216 4 3 0 0
T217 3 2 0 0
T218 6 5 0 0
T219 7 6 0 0
T220 7 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 128826 127440 0 0
T13 1 0 0 0
T23 16 14 0 0
T24 24 22 0 0
T25 14 12 0 0
T30 1 0 0 0
T33 2 1 0 0
T34 1 0 0 0
T38 2 1 0 0
T39 0 1 0 0
T43 2 1 0 0
T44 0 1 0 0
T51 576 575 0 0
T58 1 0 0 0
T80 1 0 0 0
T81 0 1 0 0
T127 1 0 0 0
T181 1 0 0 0
T182 0 1 0 0
T192 0 1 0 0
T200 0 1 0 0
T215 21 43 0 0
T216 4 11 0 0
T217 16 36 0 0
T218 10 14 0 0
T219 10 9 0 0
T220 19 18 0 0
T221 0 1 0 0
T222 24 23 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T30,T33
01CoveredT8,T30,T33
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT8,T30,T33
11CoveredT8,T30,T33

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 780 648 0 0
selKnown1 1731 723 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 780 648 0 0
T30 4 3 0 0
T33 2 1 0 0
T34 1 0 0 0
T38 2 1 0 0
T39 2 1 0 0
T58 1 0 0 0
T80 1 0 0 0
T88 0 1 0 0
T189 3 2 0 0
T191 0 15 0 0
T192 2 1 0 0
T213 6 5 0 0
T214 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1731 723 0 0
T13 1 0 0 0
T30 1 0 0 0
T33 2 1 0 0
T34 1 0 0 0
T38 2 1 0 0
T39 0 1 0 0
T43 2 1 0 0
T44 0 1 0 0
T58 1 0 0 0
T80 1 0 0 0
T81 0 1 0 0
T127 1 0 0 0
T181 1 0 0 0
T182 0 1 0 0
T192 0 1 0 0
T200 0 1 0 0
T221 0 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T11 T12 T51 

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T51,T28
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT11,T12,T51
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT11,T51,T28

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3790 3769 0 0
selKnown1 1887 1868 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3790 3769 0 0
T11 169 168 0 0
T12 19 18 0 0
T22 1 0 0 0
T23 0 14 0 0
T28 1 0 0 0
T51 1026 1025 0 0
T125 1026 1025 0 0
T126 0 1025 0 0
T223 166 165 0 0
T224 19 18 0 0
T225 189 188 0 0
T226 19 18 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1887 1868 0 0
T23 8 7 0 0
T24 13 12 0 0
T25 9 8 0 0
T51 576 575 0 0
T125 576 575 0 0
T126 576 575 0 0
T215 0 23 0 0
T216 0 8 0 0
T217 0 21 0 0
T218 0 5 0 0
T223 1 0 0 0
T224 1 0 0 0
T225 1 0 0 0
T226 1 0 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T8 T51 T28 

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T22,T23
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T51,T28
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT28,T22,T23

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 48 36 0 0
selKnown1 134 118 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 48 36 0 0
T23 3 2 0 0
T24 7 6 0 0
T25 4 3 0 0
T215 4 3 0 0
T216 4 3 0 0
T217 3 2 0 0
T218 6 5 0 0
T219 7 6 0 0
T220 7 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 134 118 0 0
T23 8 7 0 0
T24 11 10 0 0
T25 5 4 0 0
T215 21 20 0 0
T216 4 3 0 0
T217 16 15 0 0
T218 10 9 0 0
T219 10 9 0 0
T220 19 18 0 0
T222 24 23 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T10 T11 T12 

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T51,T28
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT10,T51,T45
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT11,T51,T28

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3827 3807 0 0
selKnown1 135 119 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3827 3807 0 0
T11 181 180 0 0
T12 19 18 0 0
T23 0 15 0 0
T28 1 0 0 0
T51 1025 1024 0 0
T125 1025 1024 0 0
T126 1026 1025 0 0
T223 172 171 0 0
T224 19 18 0 0
T225 205 204 0 0
T226 19 18 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 135 119 0 0
T23 11 10 0 0
T24 7 6 0 0
T25 9 8 0 0
T45 1 0 0 0
T46 1 0 0 0
T51 2 1 0 0
T125 2 1 0 0
T126 2 1 0 0
T215 16 15 0 0
T216 11 10 0 0
T217 0 8 0 0
T218 0 6 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T51 T28 T22 

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T22,T23
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT51,T28,T22
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT28,T22,T23

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 58 46 0 0
selKnown1 117 102 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 58 46 0 0
T23 6 5 0 0
T24 9 8 0 0
T25 5 4 0 0
T215 4 3 0 0
T216 9 8 0 0
T217 2 1 0 0
T218 6 5 0 0
T219 4 3 0 0
T220 9 8 0 0
T222 2 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 117 102 0 0
T23 6 5 0 0
T24 5 4 0 0
T25 5 4 0 0
T215 15 14 0 0
T216 12 11 0 0
T217 14 13 0 0
T218 7 6 0 0
T219 10 9 0 0
T220 17 16 0 0
T222 21 20 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T8 T13 T11 

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T11,T12
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T51,T22
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT13,T11,T12

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4129 4107 0 0
selKnown1 500 485 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4129 4107 0 0
T11 287 286 0 0
T12 1 0 0 0
T23 0 14 0 0
T24 0 21 0 0
T25 0 9 0 0
T51 1025 1024 0 0
T78 1 0 0 0
T79 1 0 0 0
T125 1025 1024 0 0
T126 0 1024 0 0
T215 0 16 0 0
T223 277 276 0 0
T224 1 0 0 0
T225 346 345 0 0
T226 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 500 485 0 0
T22 1 0 0 0
T23 11 10 0 0
T24 13 12 0 0
T25 8 7 0 0
T51 117 116 0 0
T125 117 116 0 0
T126 116 115 0 0
T215 18 17 0 0
T216 6 5 0 0
T217 28 27 0 0
T218 0 5 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T8 T13 T11 

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T13,T11
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T51,T22
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT8,T13,T11

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 68 48 0 0
selKnown1 124 109 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 68 48 0 0
T11 3 2 0 0
T23 5 4 0 0
T24 12 11 0 0
T25 0 1 0 0
T51 1 0 0 0
T78 1 0 0 0
T79 1 0 0 0
T125 1 0 0 0
T126 1 0 0 0
T215 0 4 0 0
T216 0 1 0 0
T217 0 3 0 0
T218 0 8 0 0
T223 3 2 0 0
T225 3 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 124 109 0 0
T23 9 8 0 0
T24 11 10 0 0
T25 7 6 0 0
T215 19 18 0 0
T216 3 2 0 0
T217 21 20 0 0
T218 8 7 0 0
T219 13 12 0 0
T220 12 11 0 0
T222 16 15 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T13 T11 T12 

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T11,T12
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT22,T23,T24
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT13,T11,T12

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4159 4137 0 0
selKnown1 133 122 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4159 4137 0 0
T11 300 299 0 0
T12 1 0 0 0
T23 0 15 0 0
T24 0 21 0 0
T25 0 15 0 0
T51 1025 1024 0 0
T78 1 0 0 0
T79 1 0 0 0
T125 1025 1024 0 0
T126 0 1025 0 0
T215 0 12 0 0
T223 282 281 0 0
T224 1 0 0 0
T225 361 360 0 0
T226 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 133 122 0 0
T23 5 4 0 0
T24 7 6 0 0
T25 7 6 0 0
T215 14 13 0 0
T216 9 8 0 0
T217 19 18 0 0
T218 6 5 0 0
T219 13 12 0 0
T220 30 29 0 0
T222 22 21 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T8 T13 T11 

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T13,T11
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT51,T28,T22
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT8,T13,T11

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 73 52 0 0
selKnown1 120 105 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 73 52 0 0
T11 3 2 0 0
T22 1 0 0 0
T23 2 1 0 0
T24 0 10 0 0
T25 0 4 0 0
T51 1 0 0 0
T78 1 0 0 0
T79 1 0 0 0
T125 1 0 0 0
T126 1 0 0 0
T215 0 1 0 0
T216 0 7 0 0
T217 0 2 0 0
T218 0 3 0 0
T223 3 2 0 0
T225 3 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 120 105 0 0
T23 10 9 0 0
T24 11 10 0 0
T25 4 3 0 0
T215 11 10 0 0
T216 6 5 0 0
T217 13 12 0 0
T218 2 1 0 0
T219 13 12 0 0
T220 24 23 0 0
T222 21 20 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T8 T10 T11 

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T37,T59
01CoveredT10,T51,T45
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T10,T11
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T37,T59
11CoveredT10,T51,T45

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1927 1905 0 0
selKnown1 3613 3582 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1927 1905 0 0
T23 15 14 0 0
T24 0 23 0 0
T25 0 8 0 0
T45 1 0 0 0
T46 1 0 0 0
T51 576 575 0 0
T97 1 0 0 0
T125 576 575 0 0
T126 576 575 0 0
T215 0 22 0 0
T216 0 18 0 0
T217 0 11 0 0
T218 0 14 0 0
T227 1 0 0 0
T228 1 0 0 0
T229 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3613 3582 0 0
T11 134 133 0 0
T12 1 0 0 0
T23 0 13 0 0
T24 0 9 0 0
T25 0 6 0 0
T28 1 0 0 0
T37 1 0 0 0
T45 1 0 0 0
T51 1025 1024 0 0
T59 1 0 0 0
T97 1 0 0 0
T125 0 1024 0 0
T126 0 1024 0 0
T215 0 10 0 0
T223 132 131 0 0
T224 1 0 0 0
T225 0 151 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T8 T10 T11 

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T37,T59
01CoveredT10,T51,T45
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T10,T11
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T37,T59
11CoveredT10,T51,T45

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1924 1902 0 0
selKnown1 3611 3580 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1924 1902 0 0
T23 14 13 0 0
T24 0 23 0 0
T25 0 8 0 0
T45 1 0 0 0
T46 1 0 0 0
T51 576 575 0 0
T97 1 0 0 0
T125 576 575 0 0
T126 576 575 0 0
T215 0 25 0 0
T216 0 18 0 0
T217 0 12 0 0
T218 0 12 0 0
T227 1 0 0 0
T228 1 0 0 0
T229 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3611 3580 0 0
T11 134 133 0 0
T12 1 0 0 0
T23 0 12 0 0
T24 0 8 0 0
T25 0 6 0 0
T28 1 0 0 0
T37 1 0 0 0
T45 1 0 0 0
T51 1025 1024 0 0
T59 1 0 0 0
T97 1 0 0 0
T125 0 1024 0 0
T126 0 1024 0 0
T215 0 10 0 0
T223 132 131 0 0
T224 1 0 0 0
T225 0 151 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T8 T10 T11 

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T37,T59
01CoveredT8,T10,T11
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T10,T11
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T37,T59
11CoveredT8,T10,T11

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 187 158 0 0
selKnown1 3665 3635 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 187 158 0 0
T23 0 8 0 0
T24 0 16 0 0
T25 0 28 0 0
T45 1 0 0 0
T46 1 0 0 0
T51 2 1 0 0
T97 1 0 0 0
T125 2 1 0 0
T126 0 1 0 0
T215 0 10 0 0
T216 0 18 0 0
T217 0 16 0 0
T218 0 2 0 0
T223 1 0 0 0
T224 1 0 0 0
T225 1 0 0 0
T226 1 0 0 0
T227 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3665 3635 0 0
T11 147 146 0 0
T12 1 0 0 0
T23 0 16 0 0
T24 0 15 0 0
T25 0 6 0 0
T28 1 0 0 0
T37 1 0 0 0
T45 1 0 0 0
T51 1025 1024 0 0
T59 1 0 0 0
T97 1 0 0 0
T125 0 1024 0 0
T126 0 1025 0 0
T215 0 19 0 0
T223 137 136 0 0
T224 1 0 0 0
T225 0 166 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T8 T10 T11 

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T37,T59
01CoveredT8,T10,T11
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T10,T11
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T37,T59
11CoveredT8,T10,T11

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 184 155 0 0
selKnown1 3664 3634 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 184 155 0 0
T23 0 7 0 0
T24 0 17 0 0
T25 0 26 0 0
T45 1 0 0 0
T46 1 0 0 0
T51 2 1 0 0
T97 1 0 0 0
T125 2 1 0 0
T126 0 1 0 0
T215 0 11 0 0
T216 0 18 0 0
T217 0 16 0 0
T218 0 3 0 0
T223 1 0 0 0
T224 1 0 0 0
T225 1 0 0 0
T226 1 0 0 0
T227 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3664 3634 0 0
T11 147 146 0 0
T12 1 0 0 0
T23 0 16 0 0
T24 0 15 0 0
T25 0 6 0 0
T28 1 0 0 0
T37 1 0 0 0
T45 1 0 0 0
T51 1025 1024 0 0
T59 1 0 0 0
T97 1 0 0 0
T125 0 1024 0 0
T126 0 1025 0 0
T215 0 18 0 0
T223 137 136 0 0
T224 1 0 0 0
T225 0 166 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T2 T8 T14 

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT2,T13,T37
01CoveredT2,T8,T51
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT13,T11,T51
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT2,T13,T37
11CoveredT2,T8,T51

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 574 551 0 0
selKnown1 27343 27309 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 574 551 0 0
T22 1 0 0 0
T23 10 9 0 0
T24 0 17 0 0
T25 0 28 0 0
T28 1 0 0 0
T51 117 116 0 0
T97 1 0 0 0
T125 117 116 0 0
T126 116 115 0 0
T215 0 23 0 0
T216 0 10 0 0
T217 0 37 0 0
T218 0 15 0 0
T227 1 0 0 0
T228 1 0 0 0
T229 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 27343 27309 0 0
T11 321 320 0 0
T12 18 17 0 0
T13 2 1 0 0
T14 20 19 0 0
T28 2 1 0 0
T49 20 19 0 0
T51 1025 1024 0 0
T78 2 1 0 0
T223 309 308 0 0
T224 18 17 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T2 T8 T14 

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT2,T13,T37
01CoveredT2,T8,T51
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT13,T11,T51
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT2,T13,T37
11CoveredT2,T8,T51

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 574 551 0 0
selKnown1 27343 27309 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 574 551 0 0
T22 1 0 0 0
T23 11 10 0 0
T24 0 15 0 0
T25 0 26 0 0
T28 1 0 0 0
T51 117 116 0 0
T97 1 0 0 0
T125 117 116 0 0
T126 116 115 0 0
T215 0 23 0 0
T216 0 10 0 0
T217 0 38 0 0
T218 0 15 0 0
T227 1 0 0 0
T228 1 0 0 0
T229 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 27343 27309 0 0
T11 321 320 0 0
T12 18 17 0 0
T13 2 1 0 0
T14 20 19 0 0
T28 2 1 0 0
T49 20 19 0 0
T51 1025 1024 0 0
T78 2 1 0 0
T223 309 308 0 0
T224 18 17 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T2 T8 T10 

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T31,T15
01CoveredT8,T10,T11
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT13,T11,T51
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T31,T15
11CoveredT8,T10,T11

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 365 320 0 0
selKnown1 27353 27320 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 365 320 0 0
T15 8 7 0 0
T16 2 1 0 0
T17 1 0 0 0
T31 2 1 0 0
T37 1 0 0 0
T45 1 0 0 0
T51 2 1 0 0
T59 1 0 0 0
T67 31 30 0 0
T125 0 1 0 0
T223 1 0 0 0
T230 0 1 0 0
T231 0 7 0 0
T232 0 32 0 0
T233 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 27353 27320 0 0
T11 333 332 0 0
T12 18 17 0 0
T13 2 1 0 0
T14 20 19 0 0
T28 2 1 0 0
T49 20 19 0 0
T51 1024 1023 0 0
T78 2 1 0 0
T223 315 314 0 0
T224 18 17 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T2 T8 T10 

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T31,T15
01CoveredT8,T10,T11
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT13,T11,T51
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T31,T15
11CoveredT8,T10,T11

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 363 318 0 0
selKnown1 27353 27320 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 363 318 0 0
T15 8 7 0 0
T16 2 1 0 0
T17 1 0 0 0
T31 2 1 0 0
T37 1 0 0 0
T45 1 0 0 0
T51 2 1 0 0
T59 1 0 0 0
T67 31 30 0 0
T125 0 1 0 0
T223 1 0 0 0
T230 0 1 0 0
T231 0 7 0 0
T232 0 32 0 0
T233 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 27353 27320 0 0
T11 333 332 0 0
T12 18 17 0 0
T13 2 1 0 0
T14 20 19 0 0
T28 2 1 0 0
T49 20 19 0 0
T51 1024 1023 0 0
T78 2 1 0 0
T223 315 314 0 0
T224 18 17 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%