Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3885650	1			T94	78		T95	66		T96	137
values[2]	780781	1			T94	22		T95	44		T96	54
values[3]	104581	1			T161	5		T269	43		T426	89
values[4]	57011	1			T269	32		T426	70		T540	1
values[5]	39080	1			T269	17		T426	46		T639	2
values[6]	29329	1			T269	12		T426	35		T639	2
values[7]	23962	1			T269	1		T426	11		T639	2
values[8]	20613	1			T426	11		T639	2		T520	15
values[9]	18613	1			T426	18		T639	2		T520	17
values[10]	16940	1			T426	12		T639	2		T520	18
values[11]	16041	1			T426	4		T639	2		T520	28
values[12]	14852	1			T426	4		T639	2		T520	21
values[13]	13818	1			T426	8		T639	2		T520	20
values[14]	13453	1			T426	9		T639	2		T520	10
values[15]	12737	1			T426	4		T639	2		T520	4
values[16]	12468	1			T426	3		T639	2		T520	4
values[17]	11977	1			T426	1		T639	2		T520	4
values[18]	11607	1			T426	2		T639	2		T520	2
values[19]	11459	1			T426	3		T639	2		T520	3
values[20]	10887	1			T426	3		T639	2		T520	5
values[21]	10656	1			T426	6		T639	2		T520	4
values[22]	10211	1			T426	3		T639	2		T520	2
values[23]	10028	1			T426	5		T639	2		T520	2
values[24]	9559	1			T426	6		T639	2		T520	2
values[25]	9273	1			T426	6		T639	2		T520	2
values[26]	8756	1			T426	6		T639	2		T520	4
values[27]	8387	1			T426	2		T639	2		T520	6
values[28]	7913	1			T426	1		T639	2		T520	3
values[29]	7438	1			T426	2		T639	2		T520	5
values[30]	6904	1			T426	4		T639	2		T520	4
values[31]	6253	1			T426	1		T639	2		T520	2
values[32]	5777	1			T426	1		T639	2		T520	10
values[33]	5381	1			T426	1		T639	2		T520	15
values[34]	4928	1			T426	2		T639	2		T520	21
values[35]	4676	1			T426	4		T639	2		T520	15
values[36]	4390	1			T426	2		T639	2		T520	11
values[37]	4107	1			T426	1		T639	2		T520	2
values[38]	4009	1			T426	2		T639	2		T520	3
values[39]	3772	1			T426	1		T639	2		T520	5
values[40]	3743	1			T426	3		T639	2		T520	1
values[41]	3414	1			T426	2		T639	2		T520	1
values[42]	3446	1			T426	5		T639	2		T520	2
values[43]	3338	1			T426	3		T639	2		T520	1
values[44]	3335	1			T426	5		T639	2		T520	1
values[45]	3222	1			T426	6		T639	2		T520	1
values[46]	3214	1			T426	3		T639	2		T520	3
values[47]	3169	1			T426	8		T639	2		T520	1
values[48]	2962	1			T426	2		T639	2		T520	1
values[49]	2945	1			T426	1		T639	2		T520	3
values[50]	2913	1			T426	2		T639	2		T520	5
values[51]	2878	1			T426	3		T639	2		T520	3
values[52]	2847	1			T426	2		T639	2		T520	1
values[53]	2807	1			T426	1		T639	2		T520	1
values[54]	2627	1			T426	2		T639	2		T520	1
values[55]	2597	1			T426	1		T639	2		T520	1
values[56]	2605	1			T426	1		T639	3		T520	1
values[57]	2582	1			T426	2		T639	2		T520	3
values[58]	2452	1			T426	4		T639	2		T520	4
values[59]	2447	1			T426	3		T639	2		T520	5
values[60]	2489	1			T426	4		T639	2		T520	4
values[61]	2807	1			T426	3		T639	2		T520	1
values[62]	4148	1			T426	3		T639	2		T520	3
values[63]	11183	1			T426	6		T639	2		T520	11
values[64]	238500	1			T426	88		T639	368		T520	63

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4989623	1			T94	105		T95	95		T96	158
values[2]	846512	1			T94	30		T95	31		T96	29
values[3]	82634	1			T94	1		T95	2		T99	4
values[4]	14303	1			T99	2		T268	1		T270	2
values[5]	5308	1			T99	1		T270	1		T540	1
values[6]	3159	1			T541	1		T639	1		T816	1
values[7]	2304	1			T522	6		T603	27		T815	3
values[8]	2035	1			T522	5		T603	14		T815	1
values[9]	1806	1			T522	4		T603	14		T815	1
values[10]	1667	1			T522	3		T603	6		T815	1
values[11]	1515	1			T522	3		T603	5		T815	2
values[12]	1444	1			T522	3		T603	1		T815	1
values[13]	1343	1			T522	3		T815	2		T492	10
values[14]	1306	1			T522	5		T815	2		T492	6
values[15]	1324	1			T522	6		T815	2		T492	8
values[16]	1193	1			T522	3		T815	1		T492	2
values[17]	1079	1			T522	3		T815	2		T492	2
values[18]	1000	1			T522	5		T815	1		T492	2
values[19]	960	1			T522	2		T815	2		T492	6
values[20]	899	1			T522	6		T815	1		T492	4
values[21]	900	1			T522	9		T815	2		T492	9
values[22]	898	1			T522	5		T815	1		T492	14
values[23]	871	1			T522	3		T815	2		T492	6
values[24]	892	1			T522	4		T815	1		T492	5
values[25]	865	1			T522	7		T815	1		T492	6
values[26]	781	1			T522	3		T815	1		T492	16
values[27]	723	1			T522	4		T815	4		T492	5
values[28]	744	1			T522	4		T815	2		T492	6
values[29]	682	1			T522	3		T815	2		T492	9
values[30]	607	1			T522	4		T815	1		T492	4
values[31]	593	1			T522	4		T815	1		T492	1
values[32]	594	1			T522	3		T815	1		T492	4
values[33]	575	1			T522	2		T815	2		T492	5
values[34]	585	1			T522	2		T815	1		T492	5
values[35]	567	1			T522	3		T815	5		T492	1
values[36]	545	1			T522	5		T815	1		T492	1
values[37]	586	1			T522	3		T815	1		T492	2
values[38]	557	1			T522	3		T815	1		T492	3
values[39]	534	1			T522	7		T815	1		T492	1
values[40]	582	1			T522	4		T815	1		T492	1
values[41]	543	1			T522	5		T815	2		T492	4
values[42]	509	1			T522	3		T815	1		T492	6
values[43]	494	1			T522	3		T815	3		T492	12
values[44]	465	1			T522	4		T815	2		T492	2
values[45]	462	1			T522	5		T815	1		T750	6
values[46]	432	1			T522	8		T815	1		T750	1
values[47]	425	1			T522	3		T815	1		T750	3
values[48]	474	1			T522	3		T815	2		T750	2
values[49]	451	1			T522	3		T815	1		T750	1
values[50]	452	1			T522	3		T815	1		T750	1
values[51]	447	1			T522	3		T815	1		T750	2
values[52]	437	1			T522	5		T815	1		T750	2
values[53]	433	1			T522	4		T815	2		T750	1
values[54]	426	1			T522	3		T815	2		T750	4
values[55]	436	1			T522	3		T815	1		T750	2
values[56]	444	1			T522	6		T815	4		T750	4
values[57]	414	1			T522	3		T815	2		T750	1
values[58]	413	1			T522	4		T815	3		T750	2
values[59]	421	1			T522	4		T815	1		T750	2
values[60]	414	1			T522	4		T815	2		T750	3
values[61]	460	1			T522	3		T815	6		T750	1
values[62]	806	1			T522	3		T815	5		T750	1
values[63]	2957	1			T522	9		T815	28		T750	6
values[64]	30130	1			T522	218		T815	101		T750	72

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	570963	1			T94	1		T95	1		T96	1
values[2]	2847872	1			T94	69		T95	110		T96	143
values[3]	1196586	1			T94	38		T95	46		T96	49
values[4]	145676	1			T99	1		T269	70		T426	113
values[5]	74142	1			T269	52		T426	76		T540	2
values[6]	48324	1			T269	31		T426	49		T639	2
values[7]	35603	1			T269	18		T426	40		T639	2
values[8]	28750	1			T269	4		T426	28		T639	2
values[9]	24359	1			T269	1		T426	10		T639	2
values[10]	21582	1			T269	1		T426	2		T639	2
values[11]	19791	1			T426	5		T639	2		T520	46
values[12]	18372	1			T426	7		T639	2		T520	29
values[13]	17105	1			T426	4		T639	2		T520	23
values[14]	15991	1			T426	5		T639	2		T520	21
values[15]	15764	1			T426	4		T639	2		T520	13
values[16]	15153	1			T426	6		T639	2		T520	13
values[17]	14390	1			T426	1		T639	2		T520	19
values[18]	13673	1			T426	5		T639	2		T520	16
values[19]	13228	1			T426	5		T639	2		T520	14
values[20]	12730	1			T426	3		T639	2		T520	7
values[21]	12337	1			T426	2		T639	2		T520	6
values[22]	11649	1			T426	3		T639	2		T520	9
values[23]	11056	1			T426	5		T639	2		T520	12
values[24]	10830	1			T426	6		T639	2		T520	11
values[25]	10430	1			T426	2		T639	2		T520	11
values[26]	10225	1			T426	3		T639	2		T520	17
values[27]	9493	1			T426	1		T639	2		T520	22
values[28]	9023	1			T426	5		T639	2		T520	15
values[29]	8424	1			T426	1		T639	2		T520	11
values[30]	7631	1			T426	1		T639	2		T520	8
values[31]	7287	1			T426	2		T639	2		T520	2
values[32]	6668	1			T426	2		T639	2		T520	9
values[33]	6084	1			T426	4		T639	2		T520	1
values[34]	5659	1			T426	1		T639	2		T520	2
values[35]	5152	1			T426	1		T639	2		T520	4
values[36]	4819	1			T426	1		T639	2		T520	2
values[37]	4698	1			T426	1		T639	2		T520	1
values[38]	4476	1			T426	3		T639	2		T520	2
values[39]	4254	1			T426	2		T639	2		T520	3
values[40]	4048	1			T426	1		T639	2		T520	3
values[41]	3909	1			T426	3		T639	2		T520	1
values[42]	3762	1			T426	4		T639	2		T520	4
values[43]	3598	1			T426	1		T639	2		T520	3
values[44]	3436	1			T426	1		T639	2		T520	12
values[45]	3404	1			T426	1		T639	2		T520	6
values[46]	3411	1			T426	2		T639	2		T520	2
values[47]	3458	1			T426	1		T639	2		T520	1
values[48]	3315	1			T426	2		T639	2		T816	1
values[49]	3335	1			T426	8		T639	2		T816	1
values[50]	3273	1			T426	10		T639	2		T816	1
values[51]	3151	1			T426	8		T639	2		T816	1
values[52]	3147	1			T426	2		T639	2		T816	1
values[53]	3081	1			T426	2		T639	2		T816	1
values[54]	2969	1			T426	1		T639	2		T816	1
values[55]	2931	1			T426	1		T639	2		T816	1
values[56]	2901	1			T426	1		T639	2		T816	1
values[57]	2834	1			T426	1		T639	2		T816	1
values[58]	2776	1			T426	1		T639	2		T816	1
values[59]	2704	1			T426	1		T639	2		T816	1
values[60]	2742	1			T426	5		T639	2		T816	1
values[61]	2836	1			T426	5		T639	2		T816	1
values[62]	3755	1			T426	8		T639	2		T816	1
values[63]	9698	1			T426	7		T639	2		T816	1
values[64]	232026	1			T426	37		T639	358		T816	221