Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1806033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35817610

1

T1

350

T2

5330

T3

7171

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25890322	1			T1	175		T2	2177		T3	2835
values[0x0]	10219315	1			T1	175		T2	3153		T3	4336
values[0x1]	1514006	1			T1	3		T2	385		T3	342

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	471158	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37152485

1

T1

353

T2

5715

T3

7513

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17862535	1			T1	177		T2	2858		T3	3757
valid_sources[0x01]	17862676	1			T1	176		T2	2857		T3	3756
valid_sources[0x02]	30052	1			T168	89		T178	15		T846	11
valid_sources[0x03]	30935	1			T168	202		T178	11		T846	5
valid_sources[0x04]	30039	1			T226	1		T168	128		T178	16
valid_sources[0x05]	30710	1			T227	28		T168	71		T178	18
valid_sources[0x06]	30212	1			T168	95		T178	21		T846	10
valid_sources[0x07]	30615	1			T226	1		T168	122		T178	20
valid_sources[0x08]	30593	1			T225	10		T168	73		T178	26
valid_sources[0x09]	30395	1			T168	61		T178	17		T846	13
valid_sources[0x0a]	30278	1			T168	49		T178	18		T846	2
valid_sources[0x0b]	30387	1			T33	1		T226	1		T168	63
valid_sources[0x0c]	29957	1			T168	81		T178	10		T846	19
valid_sources[0x0d]	29608	1			T168	45		T178	17		T173	71
valid_sources[0x0e]	29647	1			T168	47		T178	25		T846	10
valid_sources[0x0f]	30670	1			T226	5		T168	17		T178	16
valid_sources[0x10]	34177	1			T225	29		T168	49		T178	17
valid_sources[0x11]	29843	1			T226	4		T168	40		T178	15
valid_sources[0x12]	30587	1			T168	79		T178	13		T846	3
valid_sources[0x13]	34750	1			T226	1		T168	77		T178	19
valid_sources[0x14]	37832	1			T168	81		T178	14		T846	2
valid_sources[0x15]	30590	1			T226	3		T168	83		T178	23
valid_sources[0x16]	29536	1			T226	4		T168	85		T178	15
valid_sources[0x17]	30544	1			T226	1		T168	127		T178	17
valid_sources[0x18]	30968	1			T226	2		T168	64		T178	28
valid_sources[0x19]	30120	1			T227	11		T168	69		T178	19
valid_sources[0x1a]	30522	1			T33	6		T168	177		T178	9
valid_sources[0x1b]	30853	1			T33	2		T168	85		T178	29
valid_sources[0x1c]	30087	1			T33	2		T168	80		T178	19
valid_sources[0x1d]	30445	1			T168	80		T178	23		T846	4
valid_sources[0x1e]	29880	1			T65	39		T226	4		T168	49
valid_sources[0x1f]	30469	1			T33	6		T168	107		T178	19
valid_sources[0x20]	30878	1			T33	1		T226	1		T168	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25398779

1

T1

175

T2

2177

T3

2835

values[0x0]

all_enables

biggest_size

10167334

1

T1

175

T2

3153

T3

4336

values[0x1]

all_enables

biggest_size

251497

1

T33

19

T98

23

T65

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2863218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

452166

1

T94

9

T95

16

T96

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1123360	1			T94	35		T95	34		T96	59
values[0x0]	1068048	1			T94	23		T95	32		T96	60
values[0x1]	1123976	1			T94	42		T95	44		T96	72

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2216279	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1099105

1

T94

33

T95

36

T96

74

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51113	1			T96	3		T268	1		T270	10
valid_sources[0x01]	51327	1			T94	3		T96	2		T99	1
valid_sources[0x02]	51365	1			T94	4		T95	21		T96	1
valid_sources[0x03]	51309	1			T96	1		T161	1		T268	4
valid_sources[0x04]	51245	1			T94	4		T95	4		T161	8
valid_sources[0x05]	53001	1			T94	1		T95	2		T96	5
valid_sources[0x06]	52537	1			T96	3		T161	1		T268	1
valid_sources[0x07]	50785	1			T96	1		T268	3		T270	24
valid_sources[0x08]	51321	1			T94	2		T96	3		T268	2
valid_sources[0x09]	51227	1			T94	5		T99	2		T268	3
valid_sources[0x0a]	50858	1			T96	8		T270	40		T440	7
valid_sources[0x0b]	51975	1			T94	1		T161	5		T268	4
valid_sources[0x0c]	52870	1			T94	2		T96	8		T99	2
valid_sources[0x0d]	52559	1			T94	1		T96	3		T99	1
valid_sources[0x0e]	51558	1			T94	1		T95	5		T96	2
valid_sources[0x0f]	52253	1			T96	2		T270	4		T269	4
valid_sources[0x10]	51731	1			T96	7		T161	1		T270	65
valid_sources[0x11]	51729	1			T94	4		T96	7		T99	1
valid_sources[0x12]	52437	1			T94	1		T96	8		T99	4
valid_sources[0x13]	51750	1			T94	1		T96	5		T268	3
valid_sources[0x14]	52131	1			T94	1		T95	5		T96	4
valid_sources[0x15]	51349	1			T94	1		T96	3		T161	1
valid_sources[0x16]	51375	1			T96	5		T99	1		T161	3
valid_sources[0x17]	51302	1			T99	2		T268	3		T270	26
valid_sources[0x18]	52396	1			T96	1		T99	1		T270	15
valid_sources[0x19]	52436	1			T95	1		T96	12		T99	1
valid_sources[0x1a]	53360	1			T94	6		T95	3		T96	6
valid_sources[0x1b]	51814	1			T94	1		T95	1		T96	1
valid_sources[0x1c]	52278	1			T96	6		T99	2		T268	5
valid_sources[0x1d]	51296	1			T94	1		T99	1		T161	12
valid_sources[0x1e]	51261	1			T94	2		T95	7		T96	1
valid_sources[0x1f]	51705	1			T95	1		T96	2		T99	1
valid_sources[0x20]	50946	1			T94	2		T96	1		T268	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47764

1

T94

1

T95

2

T96

2

values[0x0]

all_enables

biggest_size

356609

1

T94

6

T95

12

T96

25

values[0x1]

all_enables

biggest_size

47793

1

T94

2

T95

2

T96

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3063675	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

497087

1

T94

18

T95

9

T96

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1221808	1			T94	42		T95	45		T96	65
values[0x0]	1117319	1			T94	46		T95	39		T96	62
values[0x1]	1221635	1			T94	48		T95	44		T96	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2350024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1210738

1

T94

47

T95

35

T96

68

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55447	1			T94	1		T96	2		T99	1
valid_sources[0x01]	55277	1			T94	4		T95	6		T96	4
valid_sources[0x02]	55964	1			T94	4		T95	3		T96	2
valid_sources[0x03]	55156	1			T94	1		T95	2		T96	1
valid_sources[0x04]	56279	1			T94	13		T95	2		T96	5
valid_sources[0x05]	55744	1			T94	1		T95	4		T268	7
valid_sources[0x06]	55667	1			T95	3		T96	4		T268	2
valid_sources[0x07]	54703	1			T95	3		T96	9		T99	1
valid_sources[0x08]	55343	1			T94	4		T95	1		T96	4
valid_sources[0x09]	55150	1			T94	3		T95	5		T96	1
valid_sources[0x0a]	55384	1			T99	1		T161	2		T268	2
valid_sources[0x0b]	55621	1			T94	3		T95	2		T96	2
valid_sources[0x0c]	55169	1			T96	3		T161	1		T268	9
valid_sources[0x0d]	56319	1			T95	1		T96	6		T99	1
valid_sources[0x0e]	55024	1			T94	9		T95	1		T96	3
valid_sources[0x0f]	54764	1			T95	2		T96	2		T99	1
valid_sources[0x10]	55841	1			T96	6		T161	2		T268	2
valid_sources[0x11]	54600	1			T94	1		T95	1		T96	5
valid_sources[0x12]	55764	1			T94	2		T96	5		T161	1
valid_sources[0x13]	56144	1			T94	10		T95	5		T96	3
valid_sources[0x14]	55795	1			T96	7		T99	2		T161	4
valid_sources[0x15]	54430	1			T96	3		T99	1		T161	2
valid_sources[0x16]	56110	1			T94	2		T95	2		T96	1
valid_sources[0x17]	54812	1			T94	1		T95	1		T96	2
valid_sources[0x18]	56826	1			T94	2		T95	3		T96	1
valid_sources[0x19]	57353	1			T94	2		T96	1		T99	2
valid_sources[0x1a]	57146	1			T94	7		T95	3		T96	2
valid_sources[0x1b]	54345	1			T94	2		T95	2		T96	1
valid_sources[0x1c]	55423	1			T95	1		T96	2		T161	3
valid_sources[0x1d]	54666	1			T95	1		T96	2		T161	1
valid_sources[0x1e]	55941	1			T95	1		T96	1		T99	1
valid_sources[0x1f]	55590	1			T95	2		T96	2		T99	3
valid_sources[0x20]	54871	1			T95	4		T96	5		T99	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52552

1

T96

1

T99

1

T161

1

values[0x0]

all_enables

biggest_size

392360

1

T94

13

T95

9

T96

21

values[0x1]

all_enables

biggest_size

52175

1

T94

5

T96

3

T161

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2893110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

457668

1

T94

17

T95

18

T96

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1136676	1			T94	38		T95	48		T96	64
values[0x0]	1079077	1			T94	36		T95	52		T96	65
values[0x1]	1135025	1			T94	34		T95	57		T96	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2239795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1110983

1

T94

40

T95

55

T96

67

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52511	1			T94	1		T95	1		T96	1
valid_sources[0x01]	51462	1			T94	2		T95	2		T96	3
valid_sources[0x02]	51028	1			T94	1		T95	5		T96	1
valid_sources[0x03]	52060	1			T94	5		T96	1		T161	3
valid_sources[0x04]	51802	1			T94	1		T96	3		T270	19
valid_sources[0x05]	53006	1			T94	1		T95	1		T96	4
valid_sources[0x06]	51771	1			T94	1		T99	1		T161	1
valid_sources[0x07]	52421	1			T94	3		T95	11		T96	3
valid_sources[0x08]	52494	1			T94	2		T95	10		T96	8
valid_sources[0x09]	52131	1			T94	3		T95	2		T161	5
valid_sources[0x0a]	51995	1			T94	3		T96	1		T270	14
valid_sources[0x0b]	51631	1			T94	2		T96	4		T270	21
valid_sources[0x0c]	52390	1			T94	6		T95	2		T96	5
valid_sources[0x0d]	52058	1			T94	2		T95	6		T96	6
valid_sources[0x0e]	53580	1			T96	9		T270	21		T440	3
valid_sources[0x0f]	52106	1			T96	5		T99	1		T161	1
valid_sources[0x10]	52568	1			T95	4		T96	5		T99	1
valid_sources[0x11]	51783	1			T94	2		T95	6		T270	21
valid_sources[0x12]	52528	1			T94	1		T95	2		T96	7
valid_sources[0x13]	52293	1			T95	3		T96	3		T270	13
valid_sources[0x14]	52794	1			T94	1		T95	3		T96	4
valid_sources[0x15]	53492	1			T94	2		T96	5		T99	1
valid_sources[0x16]	51823	1			T96	1		T99	1		T268	1
valid_sources[0x17]	52129	1			T94	4		T161	2		T270	24
valid_sources[0x18]	53500	1			T94	3		T96	1		T270	19
valid_sources[0x19]	52815	1			T94	2		T95	9		T96	5
valid_sources[0x1a]	52839	1			T94	5		T95	2		T96	3
valid_sources[0x1b]	51896	1			T96	3		T99	1		T270	12
valid_sources[0x1c]	52441	1			T96	2		T161	6		T270	14
valid_sources[0x1d]	50804	1			T95	3		T96	2		T99	2
valid_sources[0x1e]	52990	1			T94	1		T96	3		T99	1
valid_sources[0x1f]	52213	1			T94	1		T96	2		T270	17
valid_sources[0x20]	52168	1			T96	5		T99	1		T270	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48607

1

T94

2

T95

1

T96

4

values[0x0]

all_enables

biggest_size

360647

1

T94

14

T95

17

T96

23

values[0x1]

all_enables

biggest_size

48414

1

T94

1

T96

5

T161

2