Unified Coverage Report :: Module :: rv_plic_gateway

Module : rv_plic_gateway

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.17	100.00	20.00			87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_plic.u_gateway	75.00	100.00	25.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_gateway

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	100.00	25.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	100.00	25.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.97	99.83	100.00	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : rv_plic_gateway

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	28	3	3	100.00
ALWAYS	33	0	0
ALWAYS	33	2	2	100.00
ALWAYS	43	3	3	100.00
ALWAYS	55	3	3	100.00

27                        always_ff @(posedge clk_i or negedge rst_ni) begin
28         2/2              if (!rst_ni) src_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
29         1/1              else         src_q <= src_i;
           Tests:       T1 T2 T3 
30                        end
31                      
32                        always_comb begin
33         1/1              for (int i = 0 ; i < N_SOURCE; i++) begin
           Tests:       T4 T5 T6 
34         1/1                set[i] = (le_i[i]) ? src_i[i] & ~src_q[i] : src_i[i] ;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                        // Interrupt pending is set by source (depends on le_i), cleared by claim_i.
39                        // Until interrupt is claimed, set doesn't affect ip_o.
40                        // RISC-V PLIC spec mentioned it can have counter for edge triggered
41                        // But skipped the feature as counter consumes substantial logic size.
42                        always_ff @(posedge clk_i or negedge rst_ni) begin
43         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
44         1/1                ip_o <= '0;
           Tests:       T1 T2 T3 
45                          end else begin
46         1/1                ip_o <= (ip_o | (set & ~ia & ~ip_o)) & (~(ip_o & claim_i));
           Tests:       T1 T2 T3 
47                          end
48                        end
49                      
50                        // Interrupt active is to control ip_o. If ip_o is set then until completed
51                        // by target, ip_o shouldn't be set by source even claim_i can clear ip_o.
52                        // ia can be cleared only when ia was set. If `set` and `complete_i` happen
53                        // at the same time, always `set` wins.
54                        always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                ia <= '0;
           Tests:       T1 T2 T3 
57                          end else begin
58         1/1                ia <= (ia | (set & ~ia)) & (~(ia & complete_i & ~ip_o));
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rv_plic_gateway

	Total	Covered	Percent
Conditions	5	1	20.00
Logical	5	1	20.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (le_i[i] ? (src_i[i] & ((~src_q[i]))) : src_i[i])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       34
 SUB-EXPRESSION (src_i[i] & ((~src_q[i])))
                 ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : rv_plic_gateway

	Line No.	Total	Covered	Percent
Branches		8	7	87.50
IF	28	2	2	100.00
TERNARY	34	2	1	50.00
IF	43	2	2	100.00
IF	55	2	2	100.00

28             if (!rst_ni) src_q <= '0;
               -1-  
               ==>
29             else         src_q <= src_i;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

34               set[i] = (le_i[i]) ? src_i[i] & ~src_q[i] : src_i[i] ;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T5,T6

43             if (!rst_ni) begin
               -1-  
44               ip_o <= '0;
                 ==>
45             end else begin
46               ip_o <= (ip_o | (set & ~ia & ~ip_o)) & (~(ip_o & claim_i));
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

55             if (!rst_ni) begin
               -1-  
56               ia <= '0;
                 ==>
57             end else begin
58               ia <= (ia | (set & ~ia)) & (~(ia & complete_i & ~ip_o));
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_gateway

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	28	3	3	100.00
ALWAYS	33	0	0
ALWAYS	33	2	2	100.00
ALWAYS	43	3	3	100.00
ALWAYS	55	3	3	100.00

27                        always_ff @(posedge clk_i or negedge rst_ni) begin
28         2/2              if (!rst_ni) src_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
29         1/1              else         src_q <= src_i;
           Tests:       T1 T2 T3 
30                        end
31                      
32                        always_comb begin
33         1/1              for (int i = 0 ; i < N_SOURCE; i++) begin
           Tests:       T4 T5 T6 
34         1/1                set[i] = (le_i[i]) ? src_i[i] & ~src_q[i] : src_i[i] ;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                        // Interrupt pending is set by source (depends on le_i), cleared by claim_i.
39                        // Until interrupt is claimed, set doesn't affect ip_o.
40                        // RISC-V PLIC spec mentioned it can have counter for edge triggered
41                        // But skipped the feature as counter consumes substantial logic size.
42                        always_ff @(posedge clk_i or negedge rst_ni) begin
43         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
44         1/1                ip_o <= '0;
           Tests:       T1 T2 T3 
45                          end else begin
46         1/1                ip_o <= (ip_o | (set & ~ia & ~ip_o)) & (~(ip_o & claim_i));
           Tests:       T1 T2 T3 
47                          end
48                        end
49                      
50                        // Interrupt active is to control ip_o. If ip_o is set then until completed
51                        // by target, ip_o shouldn't be set by source even claim_i can clear ip_o.
52                        // ia can be cleared only when ia was set. If `set` and `complete_i` happen
53                        // at the same time, always `set` wins.
54                        always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                ia <= '0;
           Tests:       T1 T2 T3 
57                          end else begin
58         1/1                ia <= (ia | (set & ~ia)) & (~(ia & complete_i & ~ip_o));
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_gateway

	Total	Covered	Percent
Conditions	4	1	25.00
Logical	4	1	25.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (le_i[i] ? (src_i[i] & ((~src_q[i]))) : src_i[i])
             ---1---

-1-	Status	Tests	Exclude Annotation
0	Covered	T4,T5,T6
1	Excluded		[UNR] The le_i input is tied off to 0 (only level interrupts supported).

 LINE       34
 SUB-EXPRESSION (src_i[i] & ((~src_q[i])))
                 ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_gateway

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	28	2	2	100.00
TERNARY	34	1	1	100.00
IF	43	2	2	100.00
IF	55	2	2	100.00

28             if (!rst_ni) src_q <= '0;
               -1-  
               ==>
29             else         src_q <= src_i;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

34               set[i] = (le_i[i]) ? src_i[i] & ~src_q[i] : src_i[i] ;
                                    -1-  
                                    ==> (Excluded)  
                                    ==>  

Branches:

-1-	Status	Tests	Exclude Annotation
1	Excluded		[UNR] The le_i input is tied off to 0 (only level interrupts supported).
0	Covered	T4,T5,T6

43             if (!rst_ni) begin
               -1-  
44               ip_o <= '0;
                 ==>
45             end else begin
46               ip_o <= (ip_o | (set & ~ia & ~ip_o)) & (~(ip_o & claim_i));
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

55             if (!rst_ni) begin
               -1-  
56               ia <= '0;
                 ==>
57             end else begin
58               ia <= (ia | (set & ~ia)) & (~(ia & complete_i & ~ip_o));
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3