Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
25.56 26.32 23.08 27.27


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 50.00 31.82 54.55


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.57 98.93 79.54 98.84 73.52 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 67.58 76.47 44.44 81.82



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
25.56 26.32 23.08 27.27


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 50.00 31.82 54.55


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.57 98.93 79.54 98.84 73.52 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 67.58 76.47 44.44 81.82



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
25.56 26.32 23.08 27.27


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 50.00 31.82 54.55


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.57 98.93 79.54 98.84 73.52 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 67.58 76.47 44.44 81.82



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
25.56 26.32 23.08 27.27


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 50.00 31.82 54.55


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.57 98.93 79.54 98.84 73.52 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 67.58 76.47 44.44 81.82



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
46.80 57.89 46.15 36.36


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.35 77.78 63.64 63.64


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.57 98.93 79.54 98.84 73.52 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 93.27 100.00 88.89 90.91



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
52.40 57.89 53.85 45.45


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.38 77.78 68.18 68.18


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.57 98.93 79.54 98.84 73.52 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 93.27 100.00 88.89 90.91



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.07 68.42 69.23 54.55


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.78 83.33 77.27 72.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.57 98.93 79.54 98.84 73.52 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 93.27 100.00 88.89 90.91



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.66 68.42 76.92 63.64


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.81 83.33 81.82 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.57 98.93 79.54 98.84 73.52 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 93.27 100.00 88.89 90.91

Line Coverage for Module : pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191578.95
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510660.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T4 T5 T6  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T4 T5 T6  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T123  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T123  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T4 T5 T6  56 1/1 cnt_en = 1'b0; Tests: T4 T5 T6  57 1/1 if (wkup_en_i) begin Tests: T4 T5 T6  58 1/1 unique case (wkup_mode_i) Tests: T4 T5 T6  59 Negedge: begin 60 1/1 aon_wkup_pulse_o = falling; Tests: T6 T78 T79  61 end 62 Edge: begin 63 1/1 aon_wkup_pulse_o = rising | falling; Tests: T6 T78 T79  64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Module : pinmux_wkup
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT5,T6,T72

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT123
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT123
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00CoveredT6,T78,T79
01CoveredT6,T78,T79
10CoveredT6,T78,T79

Branch Coverage for Module : pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 8 72.73
TERNARY 50 3 2 66.67
IF 57 6 4 66.67
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T123


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Covered T6,T78,T79
1 Edge Covered T6,T78,T79
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T4,T5,T72
0 - Covered T6,T74,T78


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL19526.32
CONT_ASSIGN45100.00
CONT_ASSIGN46100.00
CONT_ASSIGN50100.00
CONT_ASSIGN52100.00
ALWAYS551000.00
ALWAYS8255100.00

44 logic rising, falling; 45 0/1 ==> assign falling = ~filter_out_d & filter_out_q; 46 0/1 ==> assign rising = filter_out_d & ~filter_out_q; 47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 0/1 ==> assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; 51 52 0/1 ==> assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); 53 54 always_comb begin : p_mode 55 0/1 ==> aon_wkup_pulse_o = 1'b0; 56 0/1 ==> cnt_en = 1'b0; 57 0/1 ==> if (wkup_en_i) begin 58 0/1 ==> unique case (wkup_mode_i) 59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end ==> MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup
TotalCoveredPercent
Conditions13323.08
Logical13323.08
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 3 27.27
TERNARY 50 3 1 33.33
IF 57 6 0 0.00
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Not Covered


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Not Covered
0 - Not Covered


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL19526.32
CONT_ASSIGN45100.00
CONT_ASSIGN46100.00
CONT_ASSIGN50100.00
CONT_ASSIGN52100.00
ALWAYS551000.00
ALWAYS8255100.00

44 logic rising, falling; 45 0/1 ==> assign falling = ~filter_out_d & filter_out_q; 46 0/1 ==> assign rising = filter_out_d & ~filter_out_q; 47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 0/1 ==> assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; 51 52 0/1 ==> assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); 53 54 always_comb begin : p_mode 55 0/1 ==> aon_wkup_pulse_o = 1'b0; 56 0/1 ==> cnt_en = 1'b0; 57 0/1 ==> if (wkup_en_i) begin 58 0/1 ==> unique case (wkup_mode_i) 59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end ==> MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup
TotalCoveredPercent
Conditions13323.08
Logical13323.08
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 3 27.27
TERNARY 50 3 1 33.33
IF 57 6 0 0.00
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Not Covered


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Not Covered
0 - Not Covered


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL19526.32
CONT_ASSIGN45100.00
CONT_ASSIGN46100.00
CONT_ASSIGN50100.00
CONT_ASSIGN52100.00
ALWAYS551000.00
ALWAYS8255100.00

44 logic rising, falling; 45 0/1 ==> assign falling = ~filter_out_d & filter_out_q; 46 0/1 ==> assign rising = filter_out_d & ~filter_out_q; 47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 0/1 ==> assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; 51 52 0/1 ==> assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); 53 54 always_comb begin : p_mode 55 0/1 ==> aon_wkup_pulse_o = 1'b0; 56 0/1 ==> cnt_en = 1'b0; 57 0/1 ==> if (wkup_en_i) begin 58 0/1 ==> unique case (wkup_mode_i) 59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end ==> MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup
TotalCoveredPercent
Conditions13323.08
Logical13323.08
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 3 27.27
TERNARY 50 3 1 33.33
IF 57 6 0 0.00
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Not Covered


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Not Covered
0 - Not Covered


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL19526.32
CONT_ASSIGN45100.00
CONT_ASSIGN46100.00
CONT_ASSIGN50100.00
CONT_ASSIGN52100.00
ALWAYS551000.00
ALWAYS8255100.00

44 logic rising, falling; 45 0/1 ==> assign falling = ~filter_out_d & filter_out_q; 46 0/1 ==> assign rising = filter_out_d & ~filter_out_q; 47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 0/1 ==> assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; 51 52 0/1 ==> assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); 53 54 always_comb begin : p_mode 55 0/1 ==> aon_wkup_pulse_o = 1'b0; 56 0/1 ==> cnt_en = 1'b0; 57 0/1 ==> if (wkup_en_i) begin 58 0/1 ==> unique case (wkup_mode_i) 59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end ==> MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup
TotalCoveredPercent
Conditions13323.08
Logical13323.08
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 3 27.27
TERNARY 50 3 1 33.33
IF 57 6 0 0.00
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Not Covered


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Not Covered
0 - Not Covered


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191157.89
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN50100.00
CONT_ASSIGN52100.00
ALWAYS5510440.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T4  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T4  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 0/1 ==> assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; 51 52 0/1 ==> assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); 53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T4  56 1/1 cnt_en = 1'b0; Tests: T4  57 1/1 if (wkup_en_i) begin Tests: T4  58 1/1 unique case (wkup_mode_i) Tests: T4  59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end ==> MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup
TotalCoveredPercent
Conditions13646.15
Logical13646.15
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT4
10CoveredT1,T2,T3
11Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4
11CoveredT4

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 4 36.36
TERNARY 50 3 1 33.33
IF 57 6 1 16.67
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Not Covered


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T4
0 - Not Covered


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191157.89
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN50100.00
CONT_ASSIGN52100.00
ALWAYS5510440.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T72 T73 T74  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T72 T73 T74  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 0/1 ==> assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; 51 52 0/1 ==> assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); 53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T72 T73 T74  56 1/1 cnt_en = 1'b0; Tests: T72 T73 T74  57 1/1 if (wkup_en_i) begin Tests: T72 T73 T74  58 1/1 unique case (wkup_mode_i) Tests: T72 T73 T74  59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup
TotalCoveredPercent
Conditions13753.85
Logical13753.85
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT72,T73,T74
10CoveredT1,T2,T3
11CoveredT72,T73,T74

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT72,T73,T74
11CoveredT72,T73,T74

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 5 45.45
TERNARY 50 3 1 33.33
IF 57 6 2 33.33
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Not Covered


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T72,T73,T74
0 - Covered T74,T124,T125


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191368.42
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510440.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T23 T71  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T23 T71  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T123  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T123  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T23 T71 T123  56 1/1 cnt_en = 1'b0; Tests: T23 T71 T123  57 1/1 if (wkup_en_i) begin Tests: T23 T71 T123  58 1/1 unique case (wkup_mode_i) Tests: T23 T71  59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup
TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT23,T71
10CoveredT1,T2,T3
11CoveredT23,T71

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T71
11CoveredT23,T71

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT123
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT123
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 6 54.55
TERNARY 50 3 2 66.67
IF 57 6 2 33.33
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T123


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T23,T71
0 - Covered T123


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191368.42
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN50100.00
CONT_ASSIGN52100.00
ALWAYS5510660.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T5 T6 T70  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T5 T6 T70  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 0/1 ==> assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; 51 52 0/1 ==> assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); 53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T5 T6 T70  56 1/1 cnt_en = 1'b0; Tests: T5 T6 T70  57 1/1 if (wkup_en_i) begin Tests: T5 T6 T70  58 1/1 unique case (wkup_mode_i) Tests: T5 T6 T70  59 Negedge: begin 60 1/1 aon_wkup_pulse_o = falling; Tests: T6 T78 T79  61 end 62 Edge: begin 63 1/1 aon_wkup_pulse_o = rising | falling; Tests: T6 T78 T79  64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup
TotalCoveredPercent
Conditions131076.92
Logical131076.92
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT5,T6,T70
10CoveredT1,T2,T3
11CoveredT5,T6,T70

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T70
11CoveredT5,T6,T70

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00CoveredT6,T78,T79
01CoveredT6,T78,T79
10CoveredT6,T78,T79

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 7 63.64
TERNARY 50 3 1 33.33
IF 57 6 4 66.67
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Not Covered


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Covered T6,T78,T79
1 Edge Covered T6,T78,T79
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T5,T70,T77
0 - Covered T6,T78,T79


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

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