Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496275351	59616455	0	0
DepthKnown_A	496275351	496171503	0	0
RvalidKnown_A	496275351	496171503	0	0
WreadyKnown_A	496275351	496171503	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	59616455	0	0
T1	42249	3485	0	0
T2	87571	9178	0	0
T3	92945	9880	0	0
T4	102283	13752	0	0
T5	128045	17042	0	0
T6	88530	11758	0	0
T25	80279	9553	0	0
T31	71614	7692	0	0
T103	86412	9024	0	0
T104	67083	7823	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496275351	45359438	0	0
DepthKnown_A	496275351	496171503	0	0
RvalidKnown_A	496275351	496171503	0	0
WreadyKnown_A	496275351	496171503	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	45359438	0	0
T1	42249	1880	0	0
T2	87571	7512	0	0
T3	92945	7323	0	0
T4	102283	10112	0	0
T5	128045	12517	0	0
T6	88530	7476	0	0
T25	80279	6756	0	0
T31	71614	5580	0	0
T103	86412	7358	0	0
T104	67083	5295	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496275351	43010295	0	0
DepthKnown_A	496275351	496171503	0	0
RvalidKnown_A	496275351	496171503	0	0
WreadyKnown_A	496275351	496171503	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	43010295	0	0
T1	42249	461	0	0
T2	87571	5828	0	0
T3	92945	7967	0	0
T4	102283	6763	0	0
T5	128045	9162	0	0
T6	88530	4832	0	0
T25	80279	4816	0	0
T31	71614	4099	0	0
T103	86412	5716	0	0
T104	67083	4989	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T33 T98 T65 
49         1/1              assign full_o = rready_i;
           Tests:       T33 T98 T65 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496275351	35750111	0	0
DepthKnown_A	496275351	496171503	0	0
RvalidKnown_A	496275351	496171503	0	0
WreadyKnown_A	496275351	496171503	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	35750111	0	0
T1	42249	353	0	0
T2	87571	5715	0	0
T3	92945	7513	0	0
T4	102283	6593	0	0
T5	128045	8829	0	0
T6	88530	4584	0	0
T25	80279	4645	0	0
T31	71614	3972	0	0
T103	86412	5603	0	0
T104	67083	4814	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496275351	496171503	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576034348	86280	0	0
DepthKnown_A	576034348	575914505	0	0
RvalidKnown_A	576034348	575914505	0	0
WreadyKnown_A	576034348	575914505	0	0
gen_passthru_fifo.paramCheckPass	2919	2919	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	86280	0	0
T1	42249	8	0	0
T2	87571	13	0	0
T3	92945	208	0	0
T4	102283	24	0	0
T5	128045	41	0	0
T6	88530	25	0	0
T25	80279	18	0	0
T31	71614	13	0	0
T103	86412	13	0	0
T104	67083	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2919	2919	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576034348	88789	0	0
DepthKnown_A	576034348	575914505	0	0
RvalidKnown_A	576034348	575914505	0	0
WreadyKnown_A	576034348	575914505	0	0
gen_passthru_fifo.paramCheckPass	2919	2919	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	88789	0	0
T1	42249	8	0	0
T2	87571	13	0	0
T3	92945	208	0	0
T4	102283	24	0	0
T5	128045	41	0	0
T6	88530	25	0	0
T25	80279	18	0	0
T31	71614	13	0	0
T103	86412	13	0	0
T104	67083	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2919	2919	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576034348	50782	0	0
DepthKnown_A	576034348	575914505	0	0
RvalidKnown_A	576034348	575914505	0	0
WreadyKnown_A	576034348	575914505	0	0
gen_passthru_fifo.paramCheckPass	2919	2919	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	50782	0	0
T1	42249	8	0	0
T2	87571	12	0	0
T3	92945	205	0	0
T4	102283	21	0	0
T5	128045	38	0	0
T6	88530	22	0	0
T25	80279	15	0	0
T31	71614	12	0	0
T103	86412	12	0	0
T104	67083	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2919	2919	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576034348	50781	0	0
DepthKnown_A	576034348	575914505	0	0
RvalidKnown_A	576034348	575914505	0	0
WreadyKnown_A	576034348	575914505	0	0
gen_passthru_fifo.paramCheckPass	2919	2919	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	50781	0	0
T1	42249	8	0	0
T2	87571	12	0	0
T3	92945	205	0	0
T4	102283	21	0	0
T5	128045	38	0	0
T6	88530	22	0	0
T25	80279	15	0	0
T31	71614	12	0	0
T103	86412	12	0	0
T104	67083	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2919	2919	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576034348	35498	0	0
DepthKnown_A	576034348	575914505	0	0
RvalidKnown_A	576034348	575914505	0	0
WreadyKnown_A	576034348	575914505	0	0
gen_passthru_fifo.paramCheckPass	2919	2919	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	35498	0	0
T2	87571	1	0	0
T3	92945	3	0	0
T4	102283	3	0	0
T5	128045	3	0	0
T6	88530	3	0	0
T25	80279	3	0	0
T28	99898	3	0	0
T31	71614	1	0	0
T103	86412	1	0	0
T104	67083	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2919	2919	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576034348	38008	0	0
DepthKnown_A	576034348	575914505	0	0
RvalidKnown_A	576034348	575914505	0	0
WreadyKnown_A	576034348	575914505	0	0
gen_passthru_fifo.paramCheckPass	2919	2919	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	38008	0	0
T2	87571	1	0	0
T3	92945	3	0	0
T4	102283	3	0	0
T5	128045	3	0	0
T6	88530	3	0	0
T25	80279	3	0	0
T28	99898	3	0	0
T31	71614	1	0	0
T103	86412	1	0	0
T104	67083	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576034348	575914505	0	0
T1	42249	42187	0	0
T2	87571	87509	0	0
T3	92945	92894	0	0
T4	102283	102225	0	0
T5	128045	127983	0	0
T6	88530	88475	0	0
T25	80279	80217	0	0
T31	71614	71552	0	0
T103	86412	86350	0	0
T104	67083	67028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2919	2919	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T25	1	1	0	0
T31	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0