Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T63,T130,T132	Yes	T63,T130,T132	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T63,T130,T132	Yes	T63,T130,T132	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T97,*T33,*T98	Yes	T97,T33,T98	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T33,T98,T65	Yes	T33,T98,T65	INPUT
tl_i.a_valid	Yes	Yes	T24,T63,T130	Yes	T24,T63,T130	INPUT
tl_o.a_ready	Yes	Yes	T24,T63,T130	Yes	T24,T63,T130	OUTPUT
tl_o.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T63,T130,T132	Yes	T63,T130,T132	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T63,T130,T132	Yes	T24,T63,T130	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T63,T130,T132	Yes	T24,T63,T130	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T53,*T54,*T55	Yes	T53,T54,T55	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T63,*T130,*T132	Yes	T63,T130,T132	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T24,T63,T130	Yes	T24,T63,T130	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T100,T101,T69	Yes	T100,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T100,T101,T102	Yes	T100,T101,T69	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	OUTPUT
cio_rx_i	Yes	Yes	T25,T41,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T63,T130,T132	Yes	T63,T130,T132	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T63,T130,T132	Yes	T63,T130,T132	OUTPUT
intr_tx_empty_o	Yes	Yes	T63,T130,T132	Yes	T63,T130,T132	OUTPUT
intr_rx_watermark_o	Yes	Yes	T63,T130,T132	Yes	T63,T130,T132	OUTPUT
intr_tx_done_o	Yes	Yes	T63,T130,T132	Yes	T63,T130,T132	OUTPUT
intr_rx_overflow_o	Yes	Yes	T63,T130,T132	Yes	T63,T130,T132	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T130,T131,T219	Yes	T130,T131,T219	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T130,T131,T219	Yes	T130,T131,T219	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T97,*T33,*T98	Yes	T97,T33,T98	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T33,T98,T65	Yes	T33,T98,T65	INPUT
tl_i.a_valid	Yes	Yes	T130,T131,T75	Yes	T130,T131,T75	INPUT
tl_o.a_ready	Yes	Yes	T130,T131,T75	Yes	T130,T131,T75	OUTPUT
tl_o.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T130,T131,T324	Yes	T130,T131,T324	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T130,T131,T189	Yes	T130,T131,T75	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T130,T131,T189	Yes	T130,T131,T75	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T53,*T54,*T55	Yes	T53,T54,T55	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T99	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T130,*T131,*T324	Yes	T130,T131,T324	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T130,T131,T75	Yes	T130,T131,T75	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	OUTPUT
cio_rx_i	Yes	Yes	T41,T34,T42	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T130,T131,T53	Yes	T130,T131,T53	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T130,T131,T324	Yes	T130,T131,T324	OUTPUT
intr_tx_empty_o	Yes	Yes	T130,T131,T324	Yes	T130,T131,T324	OUTPUT
intr_rx_watermark_o	Yes	Yes	T130,T131,T324	Yes	T130,T131,T324	OUTPUT
intr_tx_done_o	Yes	Yes	T130,T131,T324	Yes	T130,T131,T324	OUTPUT
intr_rx_overflow_o	Yes	Yes	T130,T131,T324	Yes	T130,T131,T324	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T132,T324,T12	Yes	T132,T324,T12	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T132,T324,T12	Yes	T132,T324,T12	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T97,*T33,*T98	Yes	T97,T33,T98	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T33,T98,T65	Yes	T33,T98,T65	INPUT
tl_i.a_valid	Yes	Yes	T132,T75,T189	Yes	T132,T75,T189	INPUT
tl_o.a_ready	Yes	Yes	T132,T75,T189	Yes	T132,T75,T189	OUTPUT
tl_o.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T132,T324,T12	Yes	T132,T324,T12	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T132,T189,T324	Yes	T132,T75,T189	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T132,T189,T324	Yes	T132,T75,T189	OUTPUT
tl_o.d_sink	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T65,*T99,*T270	Yes	T65,T95,T96	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T132,*T324,*T12	Yes	T132,T324,T12	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T132,T75,T189	Yes	T132,T75,T189	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	OUTPUT
cio_rx_i	Yes	Yes	T25,T132,T119	Yes	T3,T25,T132	INPUT
cio_tx_o	Yes	Yes	T132,T119,T133	Yes	T132,T119,T133	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T132,T324,T119	Yes	T132,T324,T119	OUTPUT
intr_tx_empty_o	Yes	Yes	T132,T324,T119	Yes	T132,T324,T119	OUTPUT
intr_rx_watermark_o	Yes	Yes	T132,T324,T119	Yes	T132,T324,T119	OUTPUT
intr_tx_done_o	Yes	Yes	T132,T324,T119	Yes	T132,T324,T119	OUTPUT
intr_rx_overflow_o	Yes	Yes	T132,T324,T119	Yes	T132,T324,T119	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T63,T324,T64	Yes	T63,T324,T64	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T63,T324,T64	Yes	T63,T324,T64	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T97,*T33,*T98	Yes	T97,T33,T98	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T33,T98,T65	Yes	T33,T98,T65	INPUT
tl_i.a_valid	Yes	Yes	T63,T75,T189	Yes	T63,T75,T189	INPUT
tl_o.a_ready	Yes	Yes	T63,T75,T189	Yes	T63,T75,T189	OUTPUT
tl_o.d_error	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T63,T324,T64	Yes	T63,T324,T64	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T63,T189,T324	Yes	T63,T75,T189	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T63,T189,T324	Yes	T63,T75,T189	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T65,*T99,*T270	Yes	T65,T95,T96	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T63,*T324,*T64	Yes	T63,T324,T64	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T63,T75,T189	Yes	T63,T75,T189	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	OUTPUT
cio_rx_i	Yes	Yes	T63,T64,T117	Yes	T63,T64,T117	INPUT
cio_tx_o	Yes	Yes	T63,T64,T117	Yes	T63,T64,T117	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T63,T324,T64	Yes	T63,T324,T64	OUTPUT
intr_tx_empty_o	Yes	Yes	T63,T324,T64	Yes	T63,T324,T64	OUTPUT
intr_rx_watermark_o	Yes	Yes	T63,T324,T64	Yes	T63,T324,T64	OUTPUT
intr_tx_done_o	Yes	Yes	T63,T324,T64	Yes	T63,T324,T64	OUTPUT
intr_rx_overflow_o	Yes	Yes	T63,T324,T64	Yes	T63,T324,T64	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T24,T29,T324	Yes	T24,T29,T324	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T24,T29,T324	Yes	T24,T29,T324	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T97,*T33,*T98	Yes	T97,T33,T98	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T33,T98,T65	Yes	T33,T98,T65	INPUT
tl_i.a_valid	Yes	Yes	T24,T29,T75	Yes	T24,T29,T75	INPUT
tl_o.a_ready	Yes	Yes	T24,T29,T75	Yes	T24,T29,T75	OUTPUT
tl_o.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T99	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T24,T29,T324	Yes	T24,T29,T324	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T24,T29,T189	Yes	T24,T29,T75	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T24,T29,T189	Yes	T24,T29,T75	OUTPUT
tl_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T65,*T94,*T95	Yes	T65,T94,T95	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T24,*T29,*T324	Yes	T24,T29,T324	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T24,T29,T75	Yes	T24,T29,T75	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T100,T101,T69	Yes	T100,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T100,T101,T102	Yes	T100,T101,T69	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T100,T189	Yes	T75,T100,T189	OUTPUT
cio_rx_i	Yes	Yes	T24,T29,T120	Yes	T24,T29,T120	INPUT
cio_tx_o	Yes	Yes	T24,T29,T120	Yes	T24,T29,T120	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T24,T29,T324	Yes	T24,T29,T324	OUTPUT
intr_tx_empty_o	Yes	Yes	T24,T29,T324	Yes	T24,T29,T324	OUTPUT
intr_rx_watermark_o	Yes	Yes	T24,T29,T324	Yes	T24,T29,T324	OUTPUT
intr_tx_done_o	Yes	Yes	T24,T29,T324	Yes	T24,T29,T324	OUTPUT
intr_rx_overflow_o	Yes	Yes	T24,T29,T324	Yes	T24,T29,T324	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T325,T326	Yes	T324,T325,T326	OUTPUT

*Tests covering at least one bit in the range