Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T161,T268,T269	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T95,T99,T268	Yes	T99,T268,T270	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T203,T97,T53	Yes	T203,T97,T53	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T80,T203,T97	Yes	T80,T203,T97	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T33,T98,T65	Yes	T33,T98,T65	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T227,T94,T99	Yes	T227,T94,T99	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T227,T94,T95	Yes	T227,T94,T95	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T80,T82,T232	Yes	T80,T82,T232	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T41,T34,T42	Yes	T1,T2,T5	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T86,T88,T97	Yes	T86,T88,T97	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T41,T34,T42	Yes	T1,T2,T5	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T41,T34,T42	Yes	T1,T2,T5	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T86,T88,T97	Yes	T86,T88,T97	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T41,T34,T42	Yes	T1,T2,T5	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T86,T88,T97	Yes	T86,T88,T97	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T86,T88,T97	Yes	T86,T88,T97	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T86,T88,T83	Yes	T86,T88,T83	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T86,T88,T97	Yes	T86,T88,T97	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T86,*T88,*T97	Yes	T86,T88,T97	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T86,T88,T97	Yes	T86,T88,T97	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T96,T99,T161	Yes	T96,T99,T161	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T161,T268,T269	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T96,T99,T161	Yes	T95,T96,T99	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T96,T99,T161	Yes	T95,T96,T99	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T96,T99,T161	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T99,*T268,T270	Yes	T95,T96,T99	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T96,T99,T161	Yes	T96,T99,T161	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T95,*T96,*T99	Yes	T96,T99,T268	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T97,T33,T53	Yes	T97,T33,T53	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T97,T33,T53	Yes	T97,T33,T53	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T97,T33,T53	Yes	T97,T33,T53	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T97,T33,T53	Yes	T97,T33,T53	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T97,T33,T53	Yes	T97,T33,T53	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T97,*T53,*T54	Yes	T97,T53,T54	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T97,T33,T53	Yes	T97,T33,T53	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T5	Yes	T41,T34,T42	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T97,T53,T54	Yes	T97,T53,T54	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T97,T33,T53	Yes	T97,T33,T53	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T5	Yes	T41,T34,T42	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T97,*T53,*T54	Yes	T97,T53,T54	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T5	Yes	T41,T34,T42	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T97,T33,T53	Yes	T97,T33,T53	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T198,T86	Yes	T1,T198,T86	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T198,T404,T98	Yes	T198,T404,T98	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T264	Yes	T75,T76,T264	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T405,T284	Yes	T75,T405,T284	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T405,T284	Yes	T75,T405,T284	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T75,T76,T264	Yes	T75,T76,T264	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T75,T405,T284	Yes	T75,T405,T284	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T95,*T96,*T99	Yes	T95,T96,T99	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T75,T405,T284	Yes	T75,T405,T284	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T75,T405,T284	Yes	T75,T405,T284	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T94,T96,T99	Yes	T95,T96,T99	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T405,T284,T406	Yes	T405,T284,T406	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T95,T96,T99	Yes	T75,T76,T264	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T405,T284,T406	Yes	T75,T405,T284	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T96,*T99,*T270	Yes	T95,T96,T99	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T96,T99,T161	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T284,*T407,*T408	Yes	T405,T284,T406	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T75,T405,T284	Yes	T75,T405,T284	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T97,*T33,*T98	Yes	T97,T33,T98	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T33,T98,T65	Yes	T33,T98,T65	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T80,T620,T115	Yes	T80,T620,T115	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T97,*T33,*T98	Yes	T97,T33,T98	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T33,*T94,*T95	Yes	T33,T94,T95	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T221,T223	Yes	T10,T221,T223	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T33,*T99,*T270	Yes	T33,T94,T95	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T95,T99,T270	Yes	T94,T95,T96	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T11,*T388	Yes	T10,T11,T388	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T11,T388	Yes	T10,T11,T388	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T25,T388,T75	Yes	T25,T388,T75	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T25,T388,T75	Yes	T25,T388,T75	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T25,T388,T75	Yes	T25,T388,T75	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T25,T388,T75	Yes	T25,T388,T75	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T25,T388,T75	Yes	T25,T388,T75	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T25,T388,T75	Yes	T25,T388,T75	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T33,*T94,*T95	Yes	T33,T94,T95	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T25,T388,T75	Yes	T25,T388,T75	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T25,T388,T75	Yes	T25,T388,T75	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T25,T388,T127	Yes	T25,T388,T127	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T388,T127	Yes	T25,T388,T75	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T25,T388,T127	Yes	T25,T388,T127	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T96,T99,T161	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T33,*T99,*T161	Yes	T33,T94,T95	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T25,*T388,*T127	Yes	T25,T388,T127	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T25,T388,T75	Yes	T25,T388,T75	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T31,T7,T8	Yes	T31,T7,T8	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T7,T8	Yes	T31,T7,T8	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T31,T7,T8	Yes	T31,T7,T8	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T31,T7,T8	Yes	T31,T7,T8	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T65,*T94,*T95	Yes	T65,T94,T95	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T31,T7,T8	Yes	T31,T7,T8	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T31,T7,T8	Yes	T31,T7,T8	INPUT
tl_usbdev_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T31,T7,T8	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T7,T8	Yes	T7,T8,T9	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T31,T7,T8	Yes	T7,T8,T9	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T65,*T99,*T270	Yes	T65,T95,T96	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T96,T99,T161	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T7,*T8,*T9	Yes	T7,T8,T9	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T31,T7,T8	Yes	T31,T7,T8	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T226,*T94,*T95	Yes	T226,T94,T95	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T41,T34	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T3,T4,T122	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T94,T95,T99	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T226,*T95,*T99	Yes	T226,T94,T95	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T226,T94,T95	Yes	T226,T94,T95	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T226,T161,T268	Yes	T226,T94,T95	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T226,T95,T99	Yes	T226,T94,T95	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T95,T96,T99	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T226,*T94,*T95	Yes	T226,T94,T95	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T226,T94,T95	Yes	T226,T94,T95	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T41,T34	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T75,T280,T281	Yes	T75,T280,T281	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T280,T281	Yes	T75,T280,T281	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T75,T280,T281	Yes	T75,T280,T281	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T75,T280,T281	Yes	T75,T280,T281	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T75,T280,T281	Yes	T75,T280,T281	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T226,*T94,*T95	Yes	T226,T94,T95	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T280,T281,T612	Yes	T280,T281,T612	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T75,T280,T281	Yes	T75,T280,T281	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T75,T280,T281	Yes	T75,T280,T281	INPUT
tl_hmac_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T280,T281,T612	Yes	T280,T281,T612	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T280,T281,T612	Yes	T280,T281,T612	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T75,T280,T281	Yes	T280,T281,T612	INPUT
tl_hmac_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T226,*T95,*T99	Yes	T226,T94,T95	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T96	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T75,*T280,*T281	Yes	T280,T281,T612	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T75,T280,T281	Yes	T75,T280,T281	INPUT
tl_kmac_o.d_ready	Yes	Yes	T3,T41,T220	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T220,T75,T436	Yes	T220,T75,T436	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T220,T34,T233	Yes	T220,T34,T233	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T220,T34,T233	Yes	T220,T34,T233	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T220,T75,T436	Yes	T220,T75,T436	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T220,T34,T233	Yes	T220,T34,T233	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T65,*T226,*T94	Yes	T65,T226,T94	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T220,T436,T437	Yes	T220,T436,T437	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T220,T34,T233	Yes	T220,T34,T233	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T220,T34,T233	Yes	T220,T34,T233	INPUT
tl_kmac_i.d_error	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T220,T34,T233	Yes	T220,T34,T233	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T220,T34,T233	Yes	T220,T34,T233	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T220,T34,T233	Yes	T220,T34,T194	INPUT
tl_kmac_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T95,T96,T99	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T65,*T226,*T95	Yes	T65,T226,T94	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T96,T99,T161	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T220,*T34,*T233	Yes	T220,T34,T194	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T220,T34,T233	Yes	T220,T34,T233	INPUT
tl_aes_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	INPUT
tl_aes_i.d_error	Yes	Yes	T96,T99,T161	Yes	T94,T96,T99	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	INPUT
tl_aes_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T96,T99,T161	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T96,*T99,*T270	Yes	T94,T96,T99	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T94,T96,T99	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T399,*T585,*T610	Yes	T399,T585,T610	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T399,T585,T610	Yes	T399,T585,T610	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T226,*T94,*T95	Yes	T226,T94,T95	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T159,T160,T156	Yes	T159,T160,T156	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T94,T99,T161	Yes	T94,T96,T99	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T226,*T94,*T99	Yes	T226,T94,T95	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T99,T270	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T159,*T160,*T156	Yes	T159,T160,T156	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T585,T75,T159	Yes	T585,T75,T159	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T226,*T94,*T95	Yes	T226,T94,T95	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T585,T159,T278	Yes	T585,T159,T278	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T226,*T99,*T161	Yes	T226,T94,T96	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T585,*T159,*T278	Yes	T585,T159,T278	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T585,T75,T159	Yes	T585,T75,T159	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T585,T75,T159	Yes	T585,T75,T159	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T226,*T94,*T95	Yes	T226,T94,T95	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T96,T99,T161	Yes	T96,T99,T161	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T585,T159,T160	Yes	T585,T159,T160	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T226,*T99,*T270	Yes	T226,T94,T95	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T585,*T159,*T160	Yes	T585,T159,T160	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T75,T159,T160	Yes	T75,T159,T160	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T159,T160	Yes	T75,T159,T160	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T75,T159,T160	Yes	T75,T159,T160	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T75,T159,T160	Yes	T75,T159,T160	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T75,T159,T160	Yes	T75,T159,T160	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T226,*T94,*T95	Yes	T226,T94,T95	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T75,T159,T160	Yes	T75,T159,T160	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T75,T159,T160	Yes	T75,T159,T160	INPUT
tl_edn1_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T99,T161	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T159,T160,T156	Yes	T159,T160,T156	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T160,T156,T262	Yes	T75,T159,T160	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T160,T156,T262	Yes	T75,T159,T160	INPUT
tl_edn1_i.d_sink	Yes	Yes	T94,T95,T99	Yes	T95,T96,T99	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T226,*T95,*T99	Yes	T226,T94,T95	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T159,*T160,*T156	Yes	T159,T160,T156	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T75,T159,T160	Yes	T75,T159,T160	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T33,*T94,*T95	Yes	T33,T94,T95	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T96,T99,T161	Yes	T96,T99,T161	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T96,T99,T161	Yes	T95,T96,T99	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T33,*T96,*T99	Yes	T33,T94,T96	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T96,T99,T270	Yes	T96,T99,T161	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otbn_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T75,T207,T160	Yes	T75,T207,T160	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T207,T160	Yes	T75,T207,T160	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T75,T207,T160	Yes	T75,T207,T160	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T75,T207,T160	Yes	T75,T207,T160	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T75,T207,T160	Yes	T75,T207,T160	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T98,*T65,*T225	Yes	T98,T65,T225	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T75,T207,T160	Yes	T75,T207,T160	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T75,T207,T160	Yes	T75,T207,T160	INPUT
tl_otbn_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T207,T160,T156	Yes	T207,T160,T156	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T207,T160,T156	Yes	T207,T160,T156	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T75,T207,T160	Yes	T207,T160,T156	INPUT
tl_otbn_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T95,T96,T99	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T98,*T65,*T225	Yes	T98,T65,T225	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T75,*T207,*T160	Yes	T207,T160,T156	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T75,T207,T160	Yes	T75,T207,T160	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T34,T233,T75	Yes	T34,T233,T75	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T34,T233,T75	Yes	T34,T233,T75	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T34,T233,T75	Yes	T34,T233,T75	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T34,T75,T194	Yes	T34,T75,T194	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T34,T233,T75	Yes	T34,T233,T75	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T226,*T94,*T95	Yes	T226,T94,T95	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T34,T233,T75	Yes	T34,T233,T75	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T34,T233,T75	Yes	T34,T233,T75	INPUT
tl_keymgr_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T34,T194,T234	Yes	T34,T194,T234	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T194,T234	Yes	T34,T75,T194	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T34,T194,T234	Yes	T34,T75,T194	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T226,*T95,*T99	Yes	T226,T94,T95	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T34,*T194,*T234	Yes	T34,T233,T194	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T34,T233,T75	Yes	T34,T233,T75	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T55,*T94,*T95	Yes	T55,T94,T95	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T99,*T268,*T270	Yes	T55,T94,T95	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T3,T41,T34	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T148,T201	Yes	T75,T148,T201	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T148,T201	Yes	T75,T148,T201	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T148,T201	Yes	T75,T148,T201	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T75,T148,T201	Yes	T75,T148,T201	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T75,T148,T201	Yes	T75,T148,T201	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T33,*T114,*T427	Yes	T33,T114,T427	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T75,T148,T201	Yes	T75,T148,T201	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T75,T148,T201	Yes	T75,T148,T201	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T203,T33,T316	Yes	T203,T33,T316	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T148,T201,T203	Yes	T75,T148,T201	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T148,T201,T203	Yes	T75,T148,T201	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T33,*T96,*T99	Yes	T33,T114,T427	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T148,*T201,*T203	Yes	T148,T201,T203	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T75,T148,T201	Yes	T75,T148,T201	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T41,T34	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range