Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3533065	1			T92	692		T93	103		T94	141
values[2]	710507	1			T92	153		T93	56		T94	54
values[3]	97375	1			T94	1		T156	3		T450	1
values[4]	52638	1			T433	198		T677	58		T546	11
values[5]	35352	1			T433	153		T677	32		T546	5
values[6]	27020	1			T433	93		T677	26		T824	37
values[7]	21810	1			T433	58		T677	9		T824	27
values[8]	18881	1			T433	44		T677	1		T824	15
values[9]	16651	1			T433	23		T677	1		T824	4
values[10]	14936	1			T433	20		T677	4		T824	2
values[11]	13824	1			T433	14		T677	1		T824	8
values[12]	13051	1			T433	4		T677	1		T824	10
values[13]	12440	1			T433	4		T677	1		T824	3
values[14]	11655	1			T433	3		T677	1		T824	6
values[15]	11042	1			T433	2		T677	2		T824	9
values[16]	10876	1			T433	2		T677	1		T824	11
values[17]	10325	1			T433	1		T677	3		T824	14
values[18]	10020	1			T433	1		T677	3		T824	12
values[19]	9538	1			T433	2		T677	1		T824	12
values[20]	9286	1			T433	1		T677	6		T824	9
values[21]	9046	1			T433	5		T677	3		T824	1
values[22]	8563	1			T433	5		T677	8		T825	2
values[23]	8311	1			T433	6		T677	2		T825	2
values[24]	8074	1			T433	2		T677	1		T825	2
values[25]	7608	1			T433	1		T677	1		T825	2
values[26]	7484	1			T433	1		T677	2		T825	2
values[27]	7422	1			T433	1		T677	1		T825	2
values[28]	7097	1			T433	1		T677	3		T825	2
values[29]	6460	1			T433	2		T677	1		T825	2
values[30]	6057	1			T433	1		T677	1		T825	2
values[31]	5636	1			T433	4		T677	1		T825	2
values[32]	5413	1			T433	6		T677	3		T825	2
values[33]	4892	1			T433	2		T677	1		T825	2
values[34]	4657	1			T433	2		T677	2		T825	2
values[35]	4318	1			T433	5		T677	1		T825	2
values[36]	4137	1			T433	3		T677	2		T825	2
values[37]	3907	1			T433	1		T677	3		T825	2
values[38]	3627	1			T433	2		T677	3		T825	2
values[39]	3491	1			T433	3		T677	4		T825	2
values[40]	3485	1			T433	1		T677	4		T825	2
values[41]	3343	1			T433	6		T677	5		T825	2
values[42]	3265	1			T433	4		T677	4		T825	2
values[43]	3302	1			T433	7		T677	5		T825	2
values[44]	3125	1			T433	7		T677	8		T825	2
values[45]	3141	1			T433	6		T677	2		T825	2
values[46]	3033	1			T433	3		T677	1		T825	2
values[47]	2931	1			T433	3		T677	3		T825	2
values[48]	2899	1			T433	4		T677	3		T825	2
values[49]	2877	1			T433	1		T677	2		T825	2
values[50]	2830	1			T433	1		T677	2		T825	2
values[51]	2804	1			T433	1		T677	1		T825	2
values[52]	2755	1			T433	1		T677	3		T825	2
values[53]	2651	1			T433	1		T677	3		T825	2
values[54]	2587	1			T433	1		T677	3		T825	2
values[55]	2529	1			T433	1		T677	3		T825	2
values[56]	2530	1			T433	3		T677	2		T825	2
values[57]	2451	1			T433	3		T677	2		T825	2
values[58]	2397	1			T433	1		T677	1		T825	2
values[59]	2410	1			T433	1		T677	5		T825	2
values[60]	2477	1			T433	1		T677	3		T825	2
values[61]	2588	1			T433	2		T677	1		T825	2
values[62]	3684	1			T433	9		T677	3		T825	2
values[63]	10210	1			T433	38		T677	30		T825	2
values[64]	229859	1			T433	93		T677	103		T825	372

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4515417	1			T92	692		T93	89		T94	139
values[2]	777409	1			T92	206		T93	16		T94	42
values[3]	81275	1			T92	4		T93	1		T94	9
values[4]	14365	1			T450	3		T449	3		T268	2
values[5]	5400	1			T449	2		T433	46		T677	2
values[6]	3032	1			T433	34		T677	2		T559	1
values[7]	2296	1			T433	26		T677	3		T415	1
values[8]	1891	1			T433	8		T677	3		T415	2
values[9]	1709	1			T433	3		T677	3		T415	2
values[10]	1594	1			T677	2		T415	1		T414	2
values[11]	1487	1			T677	5		T415	3		T414	3
values[12]	1443	1			T677	4		T415	3		T414	6
values[13]	1345	1			T677	4		T415	1		T414	3
values[14]	1204	1			T677	2		T415	5		T414	4
values[15]	1092	1			T677	2		T415	4		T414	3
values[16]	1092	1			T677	2		T415	1		T414	6
values[17]	1015	1			T677	2		T415	4		T414	4
values[18]	982	1			T677	3		T415	4		T414	4
values[19]	928	1			T677	2		T415	1		T414	1
values[20]	882	1			T677	1		T415	3		T414	1
values[21]	869	1			T677	2		T415	3		T414	3
values[22]	767	1			T677	2		T415	1		T414	1
values[23]	773	1			T677	2		T415	1		T414	3
values[24]	695	1			T677	3		T415	1		T414	3
values[25]	656	1			T677	4		T415	2		T414	1
values[26]	671	1			T677	4		T415	3		T414	1
values[27]	642	1			T677	3		T415	2		T414	4
values[28]	626	1			T677	1		T415	3		T414	2
values[29]	595	1			T677	2		T415	1		T414	2
values[30]	600	1			T677	1		T415	5		T414	3
values[31]	609	1			T677	2		T415	3		T414	2
values[32]	605	1			T677	1		T415	1		T414	1
values[33]	590	1			T677	1		T415	1		T414	1
values[34]	583	1			T677	1		T415	1		T414	2
values[35]	570	1			T677	1		T415	1		T414	1
values[36]	545	1			T677	2		T415	2		T414	1
values[37]	531	1			T677	3		T415	2		T414	2
values[38]	482	1			T677	3		T415	1		T414	3
values[39]	477	1			T677	2		T415	1		T414	3
values[40]	492	1			T677	3		T415	2		T414	1
values[41]	481	1			T677	2		T415	2		T414	3
values[42]	412	1			T677	1		T415	2		T414	1
values[43]	413	1			T677	2		T415	2		T414	5
values[44]	422	1			T677	1		T415	1		T414	4
values[45]	458	1			T677	1		T415	3		T414	1
values[46]	457	1			T677	1		T415	4		T414	2
values[47]	449	1			T677	1		T415	1		T414	4
values[48]	419	1			T677	1		T415	1		T414	1
values[49]	408	1			T677	1		T415	1		T414	3
values[50]	399	1			T677	1		T415	1		T414	1
values[51]	383	1			T677	1		T415	1		T414	6
values[52]	353	1			T677	1		T415	1		T414	1
values[53]	378	1			T677	1		T415	1		T414	1
values[54]	367	1			T677	1		T415	1		T414	1
values[55]	386	1			T677	2		T415	1		T414	1
values[56]	361	1			T677	5		T415	2		T414	2
values[57]	361	1			T677	1		T415	1		T414	1
values[58]	385	1			T677	3		T415	2		T414	1
values[59]	372	1			T677	5		T415	3		T414	2
values[60]	353	1			T677	2		T415	1		T414	1
values[61]	382	1			T677	1		T415	1		T414	2
values[62]	563	1			T677	12		T415	4		T414	1
values[63]	2074	1			T677	45		T415	12		T414	13
values[64]	29489	1			T677	81		T415	93		T414	150

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	519467	1			T92	6		T93	1		T94	1
values[2]	2534647	1			T92	776		T93	127		T94	28
values[3]	1136375	1			T92	226		T93	67		T94	123
values[4]	137709	1			T92	1		T94	2		T156	2
values[5]	67446	1			T433	234		T677	31		T545	4
values[6]	44879	1			T433	185		T677	47		T824	18
values[7]	32901	1			T433	139		T677	40		T824	29
values[8]	25703	1			T433	95		T677	38		T824	31
values[9]	21684	1			T433	51		T677	26		T824	27
values[10]	19257	1			T433	24		T677	13		T824	35
values[11]	17402	1			T433	13		T677	16		T824	20
values[12]	15862	1			T433	12		T677	3		T824	16
values[13]	14972	1			T433	21		T677	2		T824	17
values[14]	14242	1			T433	21		T677	2		T824	6
values[15]	13232	1			T433	6		T677	5		T824	1
values[16]	12643	1			T433	1		T677	2		T825	2
values[17]	12287	1			T433	2		T677	1		T825	2
values[18]	11783	1			T433	1		T677	1		T825	2
values[19]	11394	1			T433	7		T677	2		T825	2
values[20]	11253	1			T433	8		T677	3		T825	2
values[21]	10681	1			T433	4		T677	4		T825	2
values[22]	10469	1			T433	4		T677	3		T825	2
values[23]	9842	1			T433	2		T677	3		T825	2
values[24]	9190	1			T433	3		T677	3		T825	2
values[25]	8436	1			T433	3		T677	1		T825	2
values[26]	8063	1			T433	1		T677	1		T825	2
values[27]	7581	1			T433	2		T677	3		T825	2
values[28]	7500	1			T433	7		T677	1		T825	2
values[29]	7099	1			T433	7		T677	2		T825	2
values[30]	6830	1			T433	5		T677	1		T825	2
values[31]	6319	1			T433	2		T677	1		T825	2
values[32]	5734	1			T433	1		T677	1		T825	2
values[33]	5295	1			T433	1		T677	4		T825	2
values[34]	5068	1			T433	1		T677	1		T825	2
values[35]	4910	1			T433	1		T677	1		T825	2
values[36]	4638	1			T433	1		T677	1		T825	2
values[37]	4255	1			T433	1		T677	2		T825	2
values[38]	4114	1			T433	2		T677	1		T825	2
values[39]	3855	1			T433	3		T677	5		T825	2
values[40]	3842	1			T433	4		T677	3		T825	2
values[41]	3638	1			T433	1		T677	3		T825	2
values[42]	3343	1			T433	4		T677	6		T825	2
values[43]	3358	1			T433	5		T677	7		T825	2
values[44]	3397	1			T433	4		T677	3		T825	2
values[45]	3214	1			T433	1		T677	1		T825	2
values[46]	3237	1			T433	1		T677	1		T825	3
values[47]	3144	1			T433	2		T677	3		T825	2
values[48]	3072	1			T433	1		T677	1		T825	2
values[49]	3010	1			T433	1		T677	1		T825	2
values[50]	2943	1			T433	2		T677	1		T825	2
values[51]	2989	1			T433	3		T677	1		T825	2
values[52]	2899	1			T433	2		T677	1		T825	2
values[53]	2782	1			T433	1		T677	1		T825	2
values[54]	2800	1			T433	1		T677	5		T825	2
values[55]	2794	1			T433	2		T677	6		T825	2
values[56]	2778	1			T433	5		T677	1		T825	2
values[57]	2793	1			T433	2		T677	1		T825	2
values[58]	2743	1			T433	3		T677	1		T825	2
values[59]	2645	1			T433	2		T677	2		T825	2
values[60]	2550	1			T433	3		T677	1		T825	2
values[61]	2675	1			T433	2		T677	4		T825	2
values[62]	3491	1			T433	12		T677	4		T825	2
values[63]	8711	1			T433	32		T677	21		T825	2
values[64]	222469	1			T433	58		T677	130		T825	448