Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1727168	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35015825

1

T1

350

T2

3219

T3

2831

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25359271	1			T1	175		T2	652		T3	392
values[0x0]	9952171	1			T1	175		T2	2567		T3	2439
values[0x1]	1431551	1			T1	3		T2	65		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	496991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36246002

1

T1

353

T2

3284

T3

2859

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17376091	1			T1	177		T2	1642		T3	1430
valid_sources[0x01]	17375108	1			T1	176		T2	1642		T3	1429
valid_sources[0x02]	32595	1			T39	39		T222	1		T168	77
valid_sources[0x03]	31885	1			T168	96		T398	25		T887	1
valid_sources[0x04]	31605	1			T220	1		T222	1		T168	102
valid_sources[0x05]	31903	1			T96	1		T220	2		T222	1
valid_sources[0x06]	31249	1			T222	1		T168	87		T398	17
valid_sources[0x07]	33246	1			T95	7		T96	1		T220	1
valid_sources[0x08]	31928	1			T96	1		T220	1		T168	81
valid_sources[0x09]	31643	1			T96	1		T221	5		T222	2
valid_sources[0x0a]	32439	1			T168	114		T398	19		T887	4
valid_sources[0x0b]	41106	1			T221	1		T222	2		T168	96
valid_sources[0x0c]	31254	1			T96	4		T222	1		T168	137
valid_sources[0x0d]	32546	1			T222	2		T168	65		T398	17
valid_sources[0x0e]	31456	1			T222	1		T168	94		T398	13
valid_sources[0x0f]	32179	1			T95	2		T96	1		T168	69
valid_sources[0x10]	31748	1			T220	3		T222	1		T168	94
valid_sources[0x11]	32060	1			T220	1		T168	92		T398	23
valid_sources[0x12]	31287	1			T220	1		T168	86		T398	13
valid_sources[0x13]	32094	1			T95	3		T96	1		T220	1
valid_sources[0x14]	31996	1			T222	1		T168	99		T398	26
valid_sources[0x15]	31754	1			T220	1		T168	65		T398	18
valid_sources[0x16]	31901	1			T220	2		T222	1		T168	52
valid_sources[0x17]	32177	1			T220	1		T222	1		T168	90
valid_sources[0x18]	31988	1			T95	2		T96	4		T222	1
valid_sources[0x19]	31916	1			T168	56		T398	20		T887	2
valid_sources[0x1a]	32083	1			T220	3		T168	60		T398	18
valid_sources[0x1b]	31782	1			T220	1		T168	50		T398	22
valid_sources[0x1c]	32489	1			T95	5		T96	3		T220	1
valid_sources[0x1d]	32600	1			T168	87		T398	24		T887	4
valid_sources[0x1e]	32053	1			T96	1		T222	1		T168	95
valid_sources[0x1f]	32505	1			T96	2		T221	5		T168	70
valid_sources[0x20]	31865	1			T96	1		T220	3		T168	83

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24845437

1

T1

175

T2

652

T3

392

values[0x0]

all_enables

biggest_size

9900339

1

T1

175

T2

2567

T3

2439

values[0x1]

all_enables

biggest_size

270049

1

T39

18

T95

26

T96

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2613322	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

413459

1

T92

113

T93

27

T94

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1025069	1			T92	284		T93	55		T94	63
values[0x0]	973482	1			T92	280		T93	54		T94	67
values[0x1]	1028230	1			T92	281		T93	50		T94	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2021542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1005239

1

T92

281

T93

57

T94

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48172	1			T92	8		T93	1		T94	2
valid_sources[0x01]	47938	1			T92	10		T93	2		T94	1
valid_sources[0x02]	46214	1			T92	14		T93	2		T94	2
valid_sources[0x03]	48146	1			T92	3		T93	1		T94	5
valid_sources[0x04]	47675	1			T92	11		T93	2		T156	18
valid_sources[0x05]	47388	1			T92	13		T93	5		T94	3
valid_sources[0x06]	46692	1			T92	15		T93	3		T94	7
valid_sources[0x07]	46921	1			T92	14		T93	7		T94	4
valid_sources[0x08]	47804	1			T92	14		T93	4		T94	5
valid_sources[0x09]	47810	1			T92	7		T94	3		T156	10
valid_sources[0x0a]	47646	1			T92	8		T93	6		T94	3
valid_sources[0x0b]	46795	1			T92	11		T93	4		T94	4
valid_sources[0x0c]	46859	1			T92	9		T93	1		T94	1
valid_sources[0x0d]	48168	1			T92	18		T93	3		T94	6
valid_sources[0x0e]	47419	1			T92	14		T93	1		T94	2
valid_sources[0x0f]	46875	1			T92	32		T93	5		T94	5
valid_sources[0x10]	48400	1			T92	22		T93	2		T94	2
valid_sources[0x11]	46901	1			T92	26		T93	4		T94	3
valid_sources[0x12]	47438	1			T92	3		T93	2		T94	2
valid_sources[0x13]	46516	1			T92	18		T93	4		T94	1
valid_sources[0x14]	46818	1			T92	5		T93	1		T94	7
valid_sources[0x15]	47290	1			T92	21		T93	4		T94	2
valid_sources[0x16]	48054	1			T92	15		T93	1		T94	2
valid_sources[0x17]	47870	1			T92	23		T93	1		T94	2
valid_sources[0x18]	47522	1			T92	24		T93	1		T94	6
valid_sources[0x19]	46789	1			T92	11		T93	3		T94	2
valid_sources[0x1a]	47761	1			T92	19		T93	1		T94	2
valid_sources[0x1b]	47576	1			T92	9		T94	3		T155	2
valid_sources[0x1c]	46034	1			T92	13		T93	1		T94	1
valid_sources[0x1d]	47099	1			T92	13		T93	5		T94	2
valid_sources[0x1e]	47446	1			T92	8		T94	4		T155	1
valid_sources[0x1f]	47022	1			T92	11		T93	1		T94	5
valid_sources[0x20]	46487	1			T92	12		T93	2		T94	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43746

1

T92

9

T93

6

T94

5

values[0x0]

all_enables

biggest_size

326033

1

T92

91

T93

17

T94

23

values[0x1]

all_enables

biggest_size

43680

1

T92

13

T93

4

T94

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2780278	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

451210

1

T92

132

T93

20

T94

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1108557	1			T92	310		T93	34		T94	64
values[0x0]	1016455	1			T92	290		T93	38		T94	61
values[0x1]	1106476	1			T92	302		T93	34		T94	65

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2132945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1098543

1

T92

304

T93

42

T94

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50074	1			T92	9		T155	1		T156	1
valid_sources[0x01]	52133	1			T92	16		T156	2		T450	2
valid_sources[0x02]	49660	1			T92	14		T156	5		T450	1
valid_sources[0x03]	50490	1			T92	14		T93	1		T155	3
valid_sources[0x04]	49523	1			T92	15		T94	3		T155	1
valid_sources[0x05]	50622	1			T92	14		T93	2		T94	2
valid_sources[0x06]	49848	1			T92	15		T94	2		T155	1
valid_sources[0x07]	50954	1			T92	6		T94	10		T155	3
valid_sources[0x08]	49968	1			T92	21		T94	1		T156	1
valid_sources[0x09]	50376	1			T92	13		T156	10		T450	2
valid_sources[0x0a]	51271	1			T92	12		T93	1		T156	5
valid_sources[0x0b]	50858	1			T92	16		T156	7		T450	4
valid_sources[0x0c]	50155	1			T92	12		T94	7		T156	3
valid_sources[0x0d]	50376	1			T92	9		T93	4		T156	6
valid_sources[0x0e]	50572	1			T92	12		T93	5		T94	1
valid_sources[0x0f]	50505	1			T92	13		T93	3		T94	2
valid_sources[0x10]	50744	1			T92	10		T93	3		T156	1
valid_sources[0x11]	50919	1			T92	18		T93	3		T94	1
valid_sources[0x12]	50461	1			T92	15		T93	19		T94	10
valid_sources[0x13]	49664	1			T92	9		T155	3		T156	18
valid_sources[0x14]	50305	1			T92	12		T156	15		T450	3
valid_sources[0x15]	49182	1			T92	7		T94	3		T156	15
valid_sources[0x16]	51081	1			T92	19		T93	1		T156	7
valid_sources[0x17]	50728	1			T92	15		T93	3		T94	15
valid_sources[0x18]	49770	1			T92	9		T156	6		T449	32
valid_sources[0x19]	51227	1			T92	13		T94	23		T156	4
valid_sources[0x1a]	51573	1			T92	10		T94	1		T156	16
valid_sources[0x1b]	50327	1			T92	17		T155	1		T156	24
valid_sources[0x1c]	50745	1			T92	10		T156	18		T450	2
valid_sources[0x1d]	50995	1			T92	13		T156	5		T450	2
valid_sources[0x1e]	49891	1			T92	17		T94	7		T155	2
valid_sources[0x1f]	50183	1			T92	10		T93	3		T156	3
valid_sources[0x20]	50419	1			T92	16		T156	4		T450	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47570

1

T92

8

T93

1

T156

8

values[0x0]

all_enables

biggest_size

356301

1

T92

106

T93

17

T94

19

values[0x1]

all_enables

biggest_size

47339

1

T92

18

T93

2

T94

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2632014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

415563

1

T92

142

T93

35

T94

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1032199	1			T92	321		T93	69		T94	54
values[0x0]	980084	1			T92	347		T93	66		T94	56
values[0x1]	1035294	1			T92	341		T93	60		T94	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2036413	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1011164

1

T92

329

T93

79

T94

43

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	47997	1			T92	16		T93	4		T156	5
valid_sources[0x01]	48385	1			T92	16		T93	2		T94	3
valid_sources[0x02]	46817	1			T92	11		T155	1		T156	9
valid_sources[0x03]	48109	1			T92	28		T93	2		T449	36
valid_sources[0x04]	47670	1			T92	16		T93	2		T94	4
valid_sources[0x05]	47787	1			T92	16		T93	6		T94	1
valid_sources[0x06]	47470	1			T92	12		T94	15		T156	10
valid_sources[0x07]	48226	1			T92	21		T93	6		T94	13
valid_sources[0x08]	47795	1			T92	19		T93	1		T155	1
valid_sources[0x09]	48026	1			T92	17		T93	1		T94	9
valid_sources[0x0a]	48727	1			T92	18		T93	1		T94	9
valid_sources[0x0b]	46577	1			T92	5		T93	5		T156	12
valid_sources[0x0c]	47388	1			T92	13		T93	2		T155	1
valid_sources[0x0d]	48350	1			T92	23		T93	3		T156	12
valid_sources[0x0e]	47624	1			T92	18		T93	3		T156	5
valid_sources[0x0f]	47117	1			T92	16		T93	6		T449	31
valid_sources[0x10]	47604	1			T92	18		T93	4		T94	7
valid_sources[0x11]	47379	1			T92	21		T93	5		T94	1
valid_sources[0x12]	47583	1			T92	12		T93	6		T156	5
valid_sources[0x13]	46413	1			T92	9		T93	5		T94	4
valid_sources[0x14]	47621	1			T92	12		T93	2		T156	8
valid_sources[0x15]	47470	1			T92	11		T93	4		T94	11
valid_sources[0x16]	46827	1			T92	19		T156	9		T449	35
valid_sources[0x17]	47825	1			T92	13		T93	2		T156	7
valid_sources[0x18]	48558	1			T92	20		T94	5		T155	1
valid_sources[0x19]	47200	1			T92	17		T93	4		T155	1
valid_sources[0x1a]	48651	1			T92	25		T93	4		T155	2
valid_sources[0x1b]	47135	1			T92	17		T93	7		T94	2
valid_sources[0x1c]	46892	1			T92	12		T93	1		T94	4
valid_sources[0x1d]	48272	1			T92	20		T93	4		T156	12
valid_sources[0x1e]	48552	1			T92	12		T93	2		T94	1
valid_sources[0x1f]	46613	1			T92	9		T93	2		T94	1
valid_sources[0x20]	48329	1			T92	13		T93	3		T94	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44094

1

T92

17

T93

4

T94

4

values[0x0]

all_enables

biggest_size

327362

1

T92

104

T93

28

T94

18

values[0x1]

all_enables

biggest_size

44107

1

T92

21

T93

3

T155

1