Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_plic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.26 99.65 66.67 100.00 100.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.83 94.00 90.98 100.00 92.73 96.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_target[0].u_target 91.54 89.34 76.82 100.00 100.00
u_gateway 75.00 100.00 25.00 100.00
u_prim_flop_2sync 100.00 100.00 100.00
u_reg 96.12 94.38 99.94 90.15 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_plic
Line No.TotalCoveredPercent
TOTAL57557399.65
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Click here to see the source line report.

Cond Coverage for Module : rv_plic
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       379
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11CoveredT73,T74,T75

Toggle Coverage for Module : rv_plic
TotalCoveredPercent
Totals 33 33 100.00
Total Bits 716 716 100.00
Total Bits 0->1 358 358 100.00
Total Bits 1->0 358 358 100.00

Ports 33 33 100.00
Port Bits 716 716 100.00
Port Bits 0->1 358 358 100.00
Port Bits 1->0 358 358 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T9,T45,T27 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T9,T5,T6 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_address[27:0] Yes Yes *T92,*T94,*T155 Yes T92,T94,T155 INPUT
tl_i.a_address[29:28] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T5,*T6,*T7 Yes T5,T6,T7 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T92,*T93,*T94 Yes T92,T93,T94 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T92,T93,T94 Yes T92,T93,T94 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T92,T93,T94 Yes T92,T93,T94 INPUT
tl_i.a_valid Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_o.a_ready Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_error Yes Yes T92,T93,T94 Yes T92,T93,T94 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_sink Yes Yes T92,T93,T94 Yes T92,T93,T94 OUTPUT
tl_o.d_source[5:0] Yes Yes *T92,*T155,*T156 Yes T92,T93,T94 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T92,T93,T94 Yes T92,T93,T94 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T6,*T7 Yes T5,T6,T7 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
intr_src_i[0] Unreachable Unreachable Unreachable INPUT
intr_src_i[185:1] Yes Yes T113,T124,T315 Yes T113,T124,T315 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T73,T324,T97 Yes T73,T324,T97 INPUT
alert_rx_i[0].ping_n Yes Yes T97,T98,T329 Yes T97,T98,T329 INPUT
alert_rx_i[0].ping_p Yes Yes T97,T98,T329 Yes T97,T98,T329 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T73,T324,T97 Yes T73,T324,T97 OUTPUT
irq_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
irq_id_o[0][0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
irq_id_o[0][1] Yes Yes T5,T113,T30 Yes T5,T113,T30 OUTPUT
irq_id_o[0][2] Yes Yes T6,T113,T34 Yes T6,T113,T34 OUTPUT
irq_id_o[0][3] Yes Yes T5,T7,T113 Yes T5,T7,T113 OUTPUT
irq_id_o[0][4] Yes Yes T5,T7,T14 Yes T5,T7,T14 OUTPUT
irq_id_o[0][5] Yes Yes T5,T6,T34 Yes T5,T6,T34 OUTPUT
irq_id_o[0][6] Yes Yes T5,T34,T15 Yes T5,T34,T15 OUTPUT
irq_id_o[0][7] Yes Yes T6,T7,T45 Yes T6,T7,T45 OUTPUT
msip_o Yes Yes T269,T270,T271 Yes T269,T270,T271 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rv_plic
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 79 2 2 100.00
IF 85 2 2 100.00


79 if (claim_re[i]) claim[claim_id[i]] = 1'b1; -1- ==> MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


85 if (complete_we[i]) complete[complete_id[i]] = 1'b1; -1- ==> MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Module : rv_plic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 9 90.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 9 90.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FpvSecCmBusIntegrity_A 500805252 0 0 0
FpvSecCmRegWeOnehotCheck_A 500805252 9 0 0
Irq0Tied_A 500805252 500698652 0 0
IrqKnownO_A 500805252 500698652 0 0
MsipKnownO_A 500805252 500698652 0 0
TlAReadyKnownO_A 500805252 500698652 0 0
TlDValidKnownO_A 500805252 500698652 0 0
gen_irq_id_known[0].IrqIdKnownO_A 500805252 500698652 0 0
onehot0Claim 500805252 500698652 0 0
onehot0Complete 500805252 500698652 0 0


FpvSecCmBusIntegrity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 9 0 0
T21 605241 0 0 0
T97 121161 0 0 0
T152 66879 0 0 0
T238 505763 0 0 0
T239 211282 0 0 0
T298 0 1 0 0
T324 143117 1 0 0
T325 299640 0 0 0
T330 0 1 0 0
T331 0 1 0 0
T332 0 1 0 0
T333 0 1 0 0
T334 0 1 0 0
T335 0 1 0 0
T336 0 1 0 0
T337 277643 0 0 0
T338 97012 0 0 0
T339 383241 0 0 0

Irq0Tied_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 500698652 0 0
T1 42263 42201 0 0
T2 64373 64318 0 0
T3 57555 57497 0 0
T4 82756 82701 0 0
T5 82958 82896 0 0
T6 116647 116592 0 0
T8 82207 82149 0 0
T9 110991 110929 0 0
T31 76741 76679 0 0
T100 93929 93871 0 0

IrqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 500698652 0 0
T1 42263 42201 0 0
T2 64373 64318 0 0
T3 57555 57497 0 0
T4 82756 82701 0 0
T5 82958 82896 0 0
T6 116647 116592 0 0
T8 82207 82149 0 0
T9 110991 110929 0 0
T31 76741 76679 0 0
T100 93929 93871 0 0

MsipKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 500698652 0 0
T1 42263 42201 0 0
T2 64373 64318 0 0
T3 57555 57497 0 0
T4 82756 82701 0 0
T5 82958 82896 0 0
T6 116647 116592 0 0
T8 82207 82149 0 0
T9 110991 110929 0 0
T31 76741 76679 0 0
T100 93929 93871 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 500698652 0 0
T1 42263 42201 0 0
T2 64373 64318 0 0
T3 57555 57497 0 0
T4 82756 82701 0 0
T5 82958 82896 0 0
T6 116647 116592 0 0
T8 82207 82149 0 0
T9 110991 110929 0 0
T31 76741 76679 0 0
T100 93929 93871 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 500698652 0 0
T1 42263 42201 0 0
T2 64373 64318 0 0
T3 57555 57497 0 0
T4 82756 82701 0 0
T5 82958 82896 0 0
T6 116647 116592 0 0
T8 82207 82149 0 0
T9 110991 110929 0 0
T31 76741 76679 0 0
T100 93929 93871 0 0

gen_irq_id_known[0].IrqIdKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 500698652 0 0
T1 42263 42201 0 0
T2 64373 64318 0 0
T3 57555 57497 0 0
T4 82756 82701 0 0
T5 82958 82896 0 0
T6 116647 116592 0 0
T8 82207 82149 0 0
T9 110991 110929 0 0
T31 76741 76679 0 0
T100 93929 93871 0 0

onehot0Claim
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 500698652 0 0
T1 42263 42201 0 0
T2 64373 64318 0 0
T3 57555 57497 0 0
T4 82756 82701 0 0
T5 82958 82896 0 0
T6 116647 116592 0 0
T8 82207 82149 0 0
T9 110991 110929 0 0
T31 76741 76679 0 0
T100 93929 93871 0 0

onehot0Complete
NameAttemptsReal SuccessesFailuresIncomplete
Total 500805252 500698652 0 0
T1 42263 42201 0 0
T2 64373 64318 0 0
T3 57555 57497 0 0
T4 82756 82701 0 0
T5 82958 82896 0 0
T6 116647 116592 0 0
T8 82207 82149 0 0
T9 110991 110929 0 0
T31 76741 76679 0 0
T100 93929 93871 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%