Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T7 T14 T68
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T14,T68 |
| 1 | 0 | Covered | T7,T14,T68 |
| 1 | 1 | Covered | T7,T14,T68 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T14,T68 |
| 1 | 0 | Covered | T7,T14,T68 |
| 1 | 1 | Covered | T7,T14,T68 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
257 |
0 |
0 |
| T7 |
691 |
2 |
0 |
0 |
| T10 |
588 |
0 |
0 |
0 |
| T14 |
533 |
4 |
0 |
0 |
| T15 |
522 |
0 |
0 |
0 |
| T20 |
625 |
0 |
0 |
0 |
| T30 |
695 |
0 |
0 |
0 |
| T34 |
638 |
0 |
0 |
0 |
| T45 |
705 |
0 |
0 |
0 |
| T68 |
0 |
2 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
4 |
0 |
0 |
| T78 |
0 |
4 |
0 |
0 |
| T113 |
572 |
0 |
0 |
0 |
| T114 |
715 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
260 |
0 |
0 |
| T7 |
38892 |
2 |
0 |
0 |
| T10 |
41656 |
0 |
0 |
0 |
| T14 |
37340 |
5 |
0 |
0 |
| T15 |
38374 |
0 |
0 |
0 |
| T20 |
45302 |
0 |
0 |
0 |
| T30 |
53960 |
0 |
0 |
0 |
| T34 |
44255 |
0 |
0 |
0 |
| T45 |
56465 |
0 |
0 |
0 |
| T68 |
0 |
2 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
5 |
0 |
0 |
| T78 |
0 |
5 |
0 |
0 |
| T113 |
41320 |
0 |
0 |
0 |
| T114 |
55322 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T7 T14 T68
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T14,T68 |
| 1 | 0 | Covered | T7,T14,T68 |
| 1 | 1 | Covered | T7,T14,T68 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T14,T68 |
| 1 | 0 | Covered | T7,T14,T68 |
| 1 | 1 | Covered | T7,T14,T68 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
257 |
0 |
0 |
| T7 |
38892 |
2 |
0 |
0 |
| T10 |
41656 |
0 |
0 |
0 |
| T14 |
37340 |
4 |
0 |
0 |
| T15 |
38374 |
0 |
0 |
0 |
| T20 |
45302 |
0 |
0 |
0 |
| T30 |
53960 |
0 |
0 |
0 |
| T34 |
44255 |
0 |
0 |
0 |
| T45 |
56465 |
0 |
0 |
0 |
| T68 |
0 |
2 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
4 |
0 |
0 |
| T78 |
0 |
4 |
0 |
0 |
| T113 |
41320 |
0 |
0 |
0 |
| T114 |
55322 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
257 |
0 |
0 |
| T7 |
691 |
2 |
0 |
0 |
| T10 |
588 |
0 |
0 |
0 |
| T14 |
533 |
4 |
0 |
0 |
| T15 |
522 |
0 |
0 |
0 |
| T20 |
625 |
0 |
0 |
0 |
| T30 |
695 |
0 |
0 |
0 |
| T34 |
638 |
0 |
0 |
0 |
| T45 |
705 |
0 |
0 |
0 |
| T68 |
0 |
2 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
4 |
0 |
0 |
| T78 |
0 |
4 |
0 |
0 |
| T113 |
572 |
0 |
0 |
0 |
| T114 |
715 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
232 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
232 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
232 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
232 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
266 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
266 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
266 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
266 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
217 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
217 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
217 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
217 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T28 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T28,T168,T389 |
| 1 | 0 | Covered | T28,T168,T389 |
| 1 | 1 | Covered | T28,T390,T391 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T28,T168,T389 |
| 1 | 0 | Covered | T28,T390,T391 |
| 1 | 1 | Covered | T28,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
242 |
0 |
0 |
| T28 |
464 |
2 |
0 |
0 |
| T68 |
679 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T287 |
803 |
0 |
0 |
0 |
| T346 |
635 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T417 |
2738 |
0 |
0 |
0 |
| T418 |
2930 |
0 |
0 |
0 |
| T419 |
4854 |
0 |
0 |
0 |
| T420 |
2739 |
0 |
0 |
0 |
| T421 |
2885 |
0 |
0 |
0 |
| T422 |
2896 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
243 |
0 |
0 |
| T28 |
25487 |
3 |
0 |
0 |
| T68 |
36719 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T287 |
66340 |
0 |
0 |
0 |
| T346 |
51708 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T417 |
297096 |
0 |
0 |
0 |
| T418 |
329180 |
0 |
0 |
0 |
| T419 |
545232 |
0 |
0 |
0 |
| T420 |
298584 |
0 |
0 |
0 |
| T421 |
324160 |
0 |
0 |
0 |
| T422 |
313190 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T28 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T28,T168,T389 |
| 1 | 0 | Covered | T28,T168,T389 |
| 1 | 1 | Covered | T28,T390,T391 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T28,T168,T389 |
| 1 | 0 | Covered | T28,T390,T391 |
| 1 | 1 | Covered | T28,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
242 |
0 |
0 |
| T28 |
25487 |
2 |
0 |
0 |
| T68 |
36719 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T287 |
66340 |
0 |
0 |
0 |
| T346 |
51708 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T417 |
297096 |
0 |
0 |
0 |
| T418 |
329180 |
0 |
0 |
0 |
| T419 |
545232 |
0 |
0 |
0 |
| T420 |
298584 |
0 |
0 |
0 |
| T421 |
324160 |
0 |
0 |
0 |
| T422 |
313190 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
242 |
0 |
0 |
| T28 |
464 |
2 |
0 |
0 |
| T68 |
679 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T287 |
803 |
0 |
0 |
0 |
| T346 |
635 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T417 |
2738 |
0 |
0 |
0 |
| T418 |
2930 |
0 |
0 |
0 |
| T419 |
4854 |
0 |
0 |
0 |
| T420 |
2739 |
0 |
0 |
0 |
| T421 |
2885 |
0 |
0 |
0 |
| T422 |
2896 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T70 T71
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T70,T71 |
| 1 | 0 | Covered | T69,T70,T71 |
| 1 | 1 | Covered | T69,T70,T71 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T70,T71 |
| 1 | 0 | Covered | T69,T70,T71 |
| 1 | 1 | Covered | T69,T70,T71 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
265 |
0 |
0 |
| T69 |
1350 |
2 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T112 |
0 |
2 |
0 |
0 |
| T117 |
0 |
4 |
0 |
0 |
| T118 |
0 |
4 |
0 |
0 |
| T159 |
1159 |
0 |
0 |
0 |
| T236 |
1502 |
0 |
0 |
0 |
| T237 |
1672 |
0 |
0 |
0 |
| T306 |
1209 |
0 |
0 |
0 |
| T307 |
1350 |
0 |
0 |
0 |
| T308 |
366 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T396 |
472 |
0 |
0 |
0 |
| T403 |
0 |
2 |
0 |
0 |
| T423 |
0 |
2 |
0 |
0 |
| T424 |
0 |
2 |
0 |
0 |
| T425 |
787 |
0 |
0 |
0 |
| T426 |
494 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
265 |
0 |
0 |
| T69 |
50832 |
2 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T112 |
0 |
2 |
0 |
0 |
| T117 |
0 |
4 |
0 |
0 |
| T118 |
0 |
4 |
0 |
0 |
| T159 |
47046 |
0 |
0 |
0 |
| T236 |
125571 |
0 |
0 |
0 |
| T237 |
140660 |
0 |
0 |
0 |
| T306 |
102642 |
0 |
0 |
0 |
| T307 |
136699 |
0 |
0 |
0 |
| T308 |
22356 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T396 |
22571 |
0 |
0 |
0 |
| T403 |
0 |
2 |
0 |
0 |
| T423 |
0 |
2 |
0 |
0 |
| T424 |
0 |
2 |
0 |
0 |
| T425 |
55095 |
0 |
0 |
0 |
| T426 |
22799 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T70 T71
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T70,T71 |
| 1 | 0 | Covered | T69,T70,T71 |
| 1 | 1 | Covered | T69,T70,T71 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T70,T71 |
| 1 | 0 | Covered | T69,T70,T71 |
| 1 | 1 | Covered | T69,T70,T71 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
265 |
0 |
0 |
| T69 |
50832 |
2 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T112 |
0 |
2 |
0 |
0 |
| T117 |
0 |
4 |
0 |
0 |
| T118 |
0 |
4 |
0 |
0 |
| T159 |
47046 |
0 |
0 |
0 |
| T236 |
125571 |
0 |
0 |
0 |
| T237 |
140660 |
0 |
0 |
0 |
| T306 |
102642 |
0 |
0 |
0 |
| T307 |
136699 |
0 |
0 |
0 |
| T308 |
22356 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T396 |
22571 |
0 |
0 |
0 |
| T403 |
0 |
2 |
0 |
0 |
| T423 |
0 |
2 |
0 |
0 |
| T424 |
0 |
2 |
0 |
0 |
| T425 |
55095 |
0 |
0 |
0 |
| T426 |
22799 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
265 |
0 |
0 |
| T69 |
1350 |
2 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T112 |
0 |
2 |
0 |
0 |
| T117 |
0 |
4 |
0 |
0 |
| T118 |
0 |
4 |
0 |
0 |
| T159 |
1159 |
0 |
0 |
0 |
| T236 |
1502 |
0 |
0 |
0 |
| T237 |
1672 |
0 |
0 |
0 |
| T306 |
1209 |
0 |
0 |
0 |
| T307 |
1350 |
0 |
0 |
0 |
| T308 |
366 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T396 |
472 |
0 |
0 |
0 |
| T403 |
0 |
2 |
0 |
0 |
| T423 |
0 |
2 |
0 |
0 |
| T424 |
0 |
2 |
0 |
0 |
| T425 |
787 |
0 |
0 |
0 |
| T426 |
494 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T27 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T168,T389 |
| 1 | 0 | Covered | T27,T168,T389 |
| 1 | 1 | Covered | T27,T390,T391 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T168,T389 |
| 1 | 0 | Covered | T27,T390,T391 |
| 1 | 1 | Covered | T27,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
240 |
0 |
0 |
| T27 |
927 |
2 |
0 |
0 |
| T36 |
379 |
0 |
0 |
0 |
| T38 |
397 |
0 |
0 |
0 |
| T40 |
608 |
0 |
0 |
0 |
| T41 |
548 |
0 |
0 |
0 |
| T63 |
765 |
0 |
0 |
0 |
| T124 |
689 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T178 |
386 |
0 |
0 |
0 |
| T179 |
388 |
0 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T427 |
460 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
241 |
0 |
0 |
| T27 |
45583 |
3 |
0 |
0 |
| T36 |
15837 |
0 |
0 |
0 |
| T38 |
19268 |
0 |
0 |
0 |
| T40 |
38603 |
0 |
0 |
0 |
| T41 |
21588 |
0 |
0 |
0 |
| T63 |
59177 |
0 |
0 |
0 |
| T124 |
58557 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T178 |
18544 |
0 |
0 |
0 |
| T179 |
25109 |
0 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T427 |
21113 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T27 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T168,T389 |
| 1 | 0 | Covered | T27,T168,T389 |
| 1 | 1 | Covered | T27,T390,T391 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T168,T389 |
| 1 | 0 | Covered | T27,T390,T391 |
| 1 | 1 | Covered | T27,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
240 |
0 |
0 |
| T27 |
45583 |
2 |
0 |
0 |
| T36 |
15837 |
0 |
0 |
0 |
| T38 |
19268 |
0 |
0 |
0 |
| T40 |
38603 |
0 |
0 |
0 |
| T41 |
21588 |
0 |
0 |
0 |
| T63 |
59177 |
0 |
0 |
0 |
| T124 |
58557 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T178 |
18544 |
0 |
0 |
0 |
| T179 |
25109 |
0 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T427 |
21113 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
240 |
0 |
0 |
| T27 |
927 |
2 |
0 |
0 |
| T36 |
379 |
0 |
0 |
0 |
| T38 |
397 |
0 |
0 |
0 |
| T40 |
608 |
0 |
0 |
0 |
| T41 |
548 |
0 |
0 |
0 |
| T63 |
765 |
0 |
0 |
0 |
| T124 |
689 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T178 |
386 |
0 |
0 |
0 |
| T179 |
388 |
0 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T427 |
460 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T72 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T72,T168,T389 |
| 1 | 0 | Covered | T72,T168,T389 |
| 1 | 1 | Covered | T72,T390,T391 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T72,T168,T389 |
| 1 | 0 | Covered | T72,T390,T391 |
| 1 | 1 | Covered | T72,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
236 |
0 |
0 |
| T48 |
360 |
0 |
0 |
0 |
| T72 |
464 |
2 |
0 |
0 |
| T76 |
617 |
0 |
0 |
0 |
| T78 |
506 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T292 |
713 |
0 |
0 |
0 |
| T355 |
360 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T429 |
884 |
0 |
0 |
0 |
| T430 |
731 |
0 |
0 |
0 |
| T431 |
3295 |
0 |
0 |
0 |
| T432 |
632 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
237 |
0 |
0 |
| T48 |
19795 |
0 |
0 |
0 |
| T72 |
26672 |
3 |
0 |
0 |
| T76 |
37080 |
0 |
0 |
0 |
| T78 |
37154 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T292 |
61133 |
0 |
0 |
0 |
| T355 |
21097 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T429 |
84175 |
0 |
0 |
0 |
| T430 |
53555 |
0 |
0 |
0 |
| T431 |
364686 |
0 |
0 |
0 |
| T432 |
53748 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T72 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T72,T168,T389 |
| 1 | 0 | Covered | T72,T168,T389 |
| 1 | 1 | Covered | T72,T390,T391 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T72,T168,T389 |
| 1 | 0 | Covered | T72,T390,T391 |
| 1 | 1 | Covered | T72,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
236 |
0 |
0 |
| T48 |
19795 |
0 |
0 |
0 |
| T72 |
26672 |
2 |
0 |
0 |
| T76 |
37080 |
0 |
0 |
0 |
| T78 |
37154 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T292 |
61133 |
0 |
0 |
0 |
| T355 |
21097 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T429 |
84175 |
0 |
0 |
0 |
| T430 |
53555 |
0 |
0 |
0 |
| T431 |
364686 |
0 |
0 |
0 |
| T432 |
53748 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
236 |
0 |
0 |
| T48 |
360 |
0 |
0 |
0 |
| T72 |
464 |
2 |
0 |
0 |
| T76 |
617 |
0 |
0 |
0 |
| T78 |
506 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T292 |
713 |
0 |
0 |
0 |
| T355 |
360 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T429 |
884 |
0 |
0 |
0 |
| T430 |
731 |
0 |
0 |
0 |
| T431 |
3295 |
0 |
0 |
0 |
| T432 |
632 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T7 T14 T68
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T14,T68 |
| 1 | 0 | Covered | T7,T14,T68 |
| 1 | 1 | Covered | T14,T77,T78 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T14,T68 |
| 1 | 0 | Covered | T14,T77,T78 |
| 1 | 1 | Covered | T7,T14,T68 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
265 |
0 |
0 |
| T7 |
691 |
1 |
0 |
0 |
| T10 |
588 |
0 |
0 |
0 |
| T14 |
533 |
2 |
0 |
0 |
| T15 |
522 |
0 |
0 |
0 |
| T20 |
625 |
0 |
0 |
0 |
| T30 |
695 |
0 |
0 |
0 |
| T34 |
638 |
0 |
0 |
0 |
| T45 |
705 |
0 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T76 |
0 |
1 |
0 |
0 |
| T77 |
0 |
2 |
0 |
0 |
| T78 |
0 |
2 |
0 |
0 |
| T113 |
572 |
0 |
0 |
0 |
| T114 |
715 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
265 |
0 |
0 |
| T7 |
38892 |
1 |
0 |
0 |
| T10 |
41656 |
0 |
0 |
0 |
| T14 |
37340 |
2 |
0 |
0 |
| T15 |
38374 |
0 |
0 |
0 |
| T20 |
45302 |
0 |
0 |
0 |
| T30 |
53960 |
0 |
0 |
0 |
| T34 |
44255 |
0 |
0 |
0 |
| T45 |
56465 |
0 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T76 |
0 |
1 |
0 |
0 |
| T77 |
0 |
2 |
0 |
0 |
| T78 |
0 |
2 |
0 |
0 |
| T113 |
41320 |
0 |
0 |
0 |
| T114 |
55322 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T7 T14 T68
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T14,T68 |
| 1 | 0 | Covered | T7,T14,T68 |
| 1 | 1 | Covered | T14,T77,T78 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T14,T68 |
| 1 | 0 | Covered | T14,T77,T78 |
| 1 | 1 | Covered | T7,T14,T68 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
265 |
0 |
0 |
| T7 |
38892 |
1 |
0 |
0 |
| T10 |
41656 |
0 |
0 |
0 |
| T14 |
37340 |
2 |
0 |
0 |
| T15 |
38374 |
0 |
0 |
0 |
| T20 |
45302 |
0 |
0 |
0 |
| T30 |
53960 |
0 |
0 |
0 |
| T34 |
44255 |
0 |
0 |
0 |
| T45 |
56465 |
0 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T76 |
0 |
1 |
0 |
0 |
| T77 |
0 |
2 |
0 |
0 |
| T78 |
0 |
2 |
0 |
0 |
| T113 |
41320 |
0 |
0 |
0 |
| T114 |
55322 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
265 |
0 |
0 |
| T7 |
691 |
1 |
0 |
0 |
| T10 |
588 |
0 |
0 |
0 |
| T14 |
533 |
2 |
0 |
0 |
| T15 |
522 |
0 |
0 |
0 |
| T20 |
625 |
0 |
0 |
0 |
| T30 |
695 |
0 |
0 |
0 |
| T34 |
638 |
0 |
0 |
0 |
| T45 |
705 |
0 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T76 |
0 |
1 |
0 |
0 |
| T77 |
0 |
2 |
0 |
0 |
| T78 |
0 |
2 |
0 |
0 |
| T113 |
572 |
0 |
0 |
0 |
| T114 |
715 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
260 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
260 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
260 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
260 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
224 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
224 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
224 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
224 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
266 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
266 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
266 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
266 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T28 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T28,T168,T389 |
| 1 | 0 | Covered | T28,T168,T389 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T28,T168,T389 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T28,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
258 |
0 |
0 |
| T28 |
464 |
1 |
0 |
0 |
| T68 |
679 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T287 |
803 |
0 |
0 |
0 |
| T346 |
635 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T417 |
2738 |
0 |
0 |
0 |
| T418 |
2930 |
0 |
0 |
0 |
| T419 |
4854 |
0 |
0 |
0 |
| T420 |
2739 |
0 |
0 |
0 |
| T421 |
2885 |
0 |
0 |
0 |
| T422 |
2896 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
258 |
0 |
0 |
| T28 |
25487 |
1 |
0 |
0 |
| T68 |
36719 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T287 |
66340 |
0 |
0 |
0 |
| T346 |
51708 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T417 |
297096 |
0 |
0 |
0 |
| T418 |
329180 |
0 |
0 |
0 |
| T419 |
545232 |
0 |
0 |
0 |
| T420 |
298584 |
0 |
0 |
0 |
| T421 |
324160 |
0 |
0 |
0 |
| T422 |
313190 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T28 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T28,T168,T389 |
| 1 | 0 | Covered | T28,T168,T389 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T28,T168,T389 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T28,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
258 |
0 |
0 |
| T28 |
25487 |
1 |
0 |
0 |
| T68 |
36719 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T287 |
66340 |
0 |
0 |
0 |
| T346 |
51708 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T417 |
297096 |
0 |
0 |
0 |
| T418 |
329180 |
0 |
0 |
0 |
| T419 |
545232 |
0 |
0 |
0 |
| T420 |
298584 |
0 |
0 |
0 |
| T421 |
324160 |
0 |
0 |
0 |
| T422 |
313190 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
258 |
0 |
0 |
| T28 |
464 |
1 |
0 |
0 |
| T68 |
679 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T287 |
803 |
0 |
0 |
0 |
| T346 |
635 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T417 |
2738 |
0 |
0 |
0 |
| T418 |
2930 |
0 |
0 |
0 |
| T419 |
4854 |
0 |
0 |
0 |
| T420 |
2739 |
0 |
0 |
0 |
| T421 |
2885 |
0 |
0 |
0 |
| T422 |
2896 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T70 T71
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T70,T71 |
| 1 | 0 | Covered | T69,T70,T71 |
| 1 | 1 | Covered | T70,T117,T118 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T70,T71 |
| 1 | 0 | Covered | T70,T117,T118 |
| 1 | 1 | Covered | T69,T70,T71 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
251 |
0 |
0 |
| T69 |
1350 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
1 |
0 |
0 |
| T112 |
0 |
1 |
0 |
0 |
| T117 |
0 |
2 |
0 |
0 |
| T118 |
0 |
2 |
0 |
0 |
| T159 |
1159 |
0 |
0 |
0 |
| T236 |
1502 |
0 |
0 |
0 |
| T237 |
1672 |
0 |
0 |
0 |
| T306 |
1209 |
0 |
0 |
0 |
| T307 |
1350 |
0 |
0 |
0 |
| T308 |
366 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T396 |
472 |
0 |
0 |
0 |
| T403 |
0 |
1 |
0 |
0 |
| T423 |
0 |
1 |
0 |
0 |
| T424 |
0 |
1 |
0 |
0 |
| T425 |
787 |
0 |
0 |
0 |
| T426 |
494 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
251 |
0 |
0 |
| T69 |
50832 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
1 |
0 |
0 |
| T112 |
0 |
1 |
0 |
0 |
| T117 |
0 |
2 |
0 |
0 |
| T118 |
0 |
2 |
0 |
0 |
| T159 |
47046 |
0 |
0 |
0 |
| T236 |
125571 |
0 |
0 |
0 |
| T237 |
140660 |
0 |
0 |
0 |
| T306 |
102642 |
0 |
0 |
0 |
| T307 |
136699 |
0 |
0 |
0 |
| T308 |
22356 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T396 |
22571 |
0 |
0 |
0 |
| T403 |
0 |
1 |
0 |
0 |
| T423 |
0 |
1 |
0 |
0 |
| T424 |
0 |
1 |
0 |
0 |
| T425 |
55095 |
0 |
0 |
0 |
| T426 |
22799 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T70 T71
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T70,T71 |
| 1 | 0 | Covered | T69,T70,T71 |
| 1 | 1 | Covered | T70,T117,T118 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T70,T71 |
| 1 | 0 | Covered | T70,T117,T118 |
| 1 | 1 | Covered | T69,T70,T71 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
251 |
0 |
0 |
| T69 |
50832 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
1 |
0 |
0 |
| T112 |
0 |
1 |
0 |
0 |
| T117 |
0 |
2 |
0 |
0 |
| T118 |
0 |
2 |
0 |
0 |
| T159 |
47046 |
0 |
0 |
0 |
| T236 |
125571 |
0 |
0 |
0 |
| T237 |
140660 |
0 |
0 |
0 |
| T306 |
102642 |
0 |
0 |
0 |
| T307 |
136699 |
0 |
0 |
0 |
| T308 |
22356 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T396 |
22571 |
0 |
0 |
0 |
| T403 |
0 |
1 |
0 |
0 |
| T423 |
0 |
1 |
0 |
0 |
| T424 |
0 |
1 |
0 |
0 |
| T425 |
55095 |
0 |
0 |
0 |
| T426 |
22799 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
251 |
0 |
0 |
| T69 |
1350 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
1 |
0 |
0 |
| T112 |
0 |
1 |
0 |
0 |
| T117 |
0 |
2 |
0 |
0 |
| T118 |
0 |
2 |
0 |
0 |
| T159 |
1159 |
0 |
0 |
0 |
| T236 |
1502 |
0 |
0 |
0 |
| T237 |
1672 |
0 |
0 |
0 |
| T306 |
1209 |
0 |
0 |
0 |
| T307 |
1350 |
0 |
0 |
0 |
| T308 |
366 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T396 |
472 |
0 |
0 |
0 |
| T403 |
0 |
1 |
0 |
0 |
| T423 |
0 |
1 |
0 |
0 |
| T424 |
0 |
1 |
0 |
0 |
| T425 |
787 |
0 |
0 |
0 |
| T426 |
494 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T27 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T168,T389 |
| 1 | 0 | Covered | T27,T168,T389 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T168,T389 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T27,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
205 |
0 |
0 |
| T27 |
927 |
1 |
0 |
0 |
| T36 |
379 |
0 |
0 |
0 |
| T38 |
397 |
0 |
0 |
0 |
| T40 |
608 |
0 |
0 |
0 |
| T41 |
548 |
0 |
0 |
0 |
| T63 |
765 |
0 |
0 |
0 |
| T124 |
689 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T178 |
386 |
0 |
0 |
0 |
| T179 |
388 |
0 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T427 |
460 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
205 |
0 |
0 |
| T27 |
45583 |
1 |
0 |
0 |
| T36 |
15837 |
0 |
0 |
0 |
| T38 |
19268 |
0 |
0 |
0 |
| T40 |
38603 |
0 |
0 |
0 |
| T41 |
21588 |
0 |
0 |
0 |
| T63 |
59177 |
0 |
0 |
0 |
| T124 |
58557 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T178 |
18544 |
0 |
0 |
0 |
| T179 |
25109 |
0 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T427 |
21113 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T27 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T168,T389 |
| 1 | 0 | Covered | T27,T168,T389 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T168,T389 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T27,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
205 |
0 |
0 |
| T27 |
45583 |
1 |
0 |
0 |
| T36 |
15837 |
0 |
0 |
0 |
| T38 |
19268 |
0 |
0 |
0 |
| T40 |
38603 |
0 |
0 |
0 |
| T41 |
21588 |
0 |
0 |
0 |
| T63 |
59177 |
0 |
0 |
0 |
| T124 |
58557 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T178 |
18544 |
0 |
0 |
0 |
| T179 |
25109 |
0 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T427 |
21113 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
205 |
0 |
0 |
| T27 |
927 |
1 |
0 |
0 |
| T36 |
379 |
0 |
0 |
0 |
| T38 |
397 |
0 |
0 |
0 |
| T40 |
608 |
0 |
0 |
0 |
| T41 |
548 |
0 |
0 |
0 |
| T63 |
765 |
0 |
0 |
0 |
| T124 |
689 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T178 |
386 |
0 |
0 |
0 |
| T179 |
388 |
0 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T427 |
460 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T72 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T72,T168,T389 |
| 1 | 0 | Covered | T72,T168,T389 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T72,T168,T389 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T72,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
238 |
0 |
0 |
| T48 |
360 |
0 |
0 |
0 |
| T72 |
464 |
1 |
0 |
0 |
| T76 |
617 |
0 |
0 |
0 |
| T78 |
506 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T292 |
713 |
0 |
0 |
0 |
| T355 |
360 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T429 |
884 |
0 |
0 |
0 |
| T430 |
731 |
0 |
0 |
0 |
| T431 |
3295 |
0 |
0 |
0 |
| T432 |
632 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
239 |
0 |
0 |
| T48 |
19795 |
0 |
0 |
0 |
| T72 |
26672 |
1 |
0 |
0 |
| T76 |
37080 |
0 |
0 |
0 |
| T78 |
37154 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T292 |
61133 |
0 |
0 |
0 |
| T355 |
21097 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T429 |
84175 |
0 |
0 |
0 |
| T430 |
53555 |
0 |
0 |
0 |
| T431 |
364686 |
0 |
0 |
0 |
| T432 |
53748 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T72 T168 T389
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T72,T168,T389 |
| 1 | 0 | Covered | T72,T168,T389 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T72,T168,T389 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T72,T168,T389 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
239 |
0 |
0 |
| T48 |
19795 |
0 |
0 |
0 |
| T72 |
26672 |
1 |
0 |
0 |
| T76 |
37080 |
0 |
0 |
0 |
| T78 |
37154 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T292 |
61133 |
0 |
0 |
0 |
| T355 |
21097 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T429 |
84175 |
0 |
0 |
0 |
| T430 |
53555 |
0 |
0 |
0 |
| T431 |
364686 |
0 |
0 |
0 |
| T432 |
53748 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
239 |
0 |
0 |
| T48 |
360 |
0 |
0 |
0 |
| T72 |
464 |
1 |
0 |
0 |
| T76 |
617 |
0 |
0 |
0 |
| T78 |
506 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T292 |
713 |
0 |
0 |
0 |
| T355 |
360 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T429 |
884 |
0 |
0 |
0 |
| T430 |
731 |
0 |
0 |
0 |
| T431 |
3295 |
0 |
0 |
0 |
| T432 |
632 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
236 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
236 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
236 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
236 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T87 T115 T116
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T87,T115,T116 |
| 1 | 0 | Covered | T87,T115,T116 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T87,T115,T116 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T87,T115,T116 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
204 |
0 |
0 |
| T115 |
596 |
1 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T195 |
748 |
0 |
0 |
0 |
| T304 |
382 |
0 |
0 |
0 |
| T321 |
1072 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T411 |
0 |
2 |
0 |
0 |
| T412 |
0 |
1 |
0 |
0 |
| T625 |
941 |
0 |
0 |
0 |
| T651 |
360 |
0 |
0 |
0 |
| T652 |
822 |
0 |
0 |
0 |
| T653 |
933 |
0 |
0 |
0 |
| T654 |
1475 |
0 |
0 |
0 |
| T655 |
1731 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
206 |
0 |
0 |
| T39 |
170046 |
0 |
0 |
0 |
| T82 |
123836 |
0 |
0 |
0 |
| T87 |
38271 |
1 |
0 |
0 |
| T88 |
49828 |
0 |
0 |
0 |
| T89 |
64527 |
0 |
0 |
0 |
| T115 |
0 |
1 |
0 |
0 |
| T116 |
0 |
1 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T189 |
297420 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T434 |
307722 |
0 |
0 |
0 |
| T435 |
33477 |
0 |
0 |
0 |
| T436 |
63795 |
0 |
0 |
0 |
| T437 |
85070 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T87 T115 T116
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T87,T115,T116 |
| 1 | 0 | Covered | T115,T168,T389 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T87,T115,T116 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T87,T115,T116 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
206 |
0 |
0 |
| T39 |
170046 |
0 |
0 |
0 |
| T82 |
123836 |
0 |
0 |
0 |
| T87 |
38271 |
1 |
0 |
0 |
| T88 |
49828 |
0 |
0 |
0 |
| T89 |
64527 |
0 |
0 |
0 |
| T115 |
0 |
1 |
0 |
0 |
| T116 |
0 |
1 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T189 |
297420 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T434 |
307722 |
0 |
0 |
0 |
| T435 |
33477 |
0 |
0 |
0 |
| T436 |
63795 |
0 |
0 |
0 |
| T437 |
85070 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
206 |
0 |
0 |
| T39 |
1794 |
0 |
0 |
0 |
| T82 |
1269 |
0 |
0 |
0 |
| T87 |
811 |
1 |
0 |
0 |
| T88 |
1148 |
0 |
0 |
0 |
| T89 |
821 |
0 |
0 |
0 |
| T115 |
0 |
1 |
0 |
0 |
| T116 |
0 |
1 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T184 |
0 |
1 |
0 |
0 |
| T189 |
6342 |
0 |
0 |
0 |
| T389 |
0 |
1 |
0 |
0 |
| T390 |
0 |
2 |
0 |
0 |
| T391 |
0 |
2 |
0 |
0 |
| T409 |
0 |
1 |
0 |
0 |
| T410 |
0 |
2 |
0 |
0 |
| T434 |
4990 |
0 |
0 |
0 |
| T435 |
490 |
0 |
0 |
0 |
| T436 |
910 |
0 |
0 |
0 |
| T437 |
1263 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
253 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
253 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T168 T389 T162
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T168,T389,T162 |
| 1 | 1 | Covered | T390,T391,T411 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T168,T389,T162 |
| 1 | 0 | Covered | T390,T391,T411 |
| 1 | 1 | Covered | T168,T389,T162 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145539830 |
253 |
0 |
0 |
| T174 |
69798 |
1 |
0 |
0 |
| T184 |
73267 |
1 |
0 |
0 |
| T389 |
47548 |
1 |
0 |
0 |
| T390 |
75639 |
2 |
0 |
0 |
| T391 |
83342 |
2 |
0 |
0 |
| T409 |
49463 |
1 |
0 |
0 |
| T410 |
118887 |
2 |
0 |
0 |
| T411 |
92502 |
2 |
0 |
0 |
| T412 |
45050 |
1 |
0 |
0 |
| T413 |
135163 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1726154 |
253 |
0 |
0 |
| T174 |
1271 |
1 |
0 |
0 |
| T184 |
1028 |
1 |
0 |
0 |
| T389 |
723 |
1 |
0 |
0 |
| T390 |
907 |
2 |
0 |
0 |
| T391 |
954 |
2 |
0 |
0 |
| T409 |
650 |
1 |
0 |
0 |
| T410 |
2268 |
2 |
0 |
0 |
| T411 |
1084 |
2 |
0 |
0 |
| T412 |
671 |
1 |
0 |
0 |
| T413 |
1771 |
2 |
0 |
0 |