Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500805252	59951783	0	0
DepthKnown_A	500805252	500698652	0	0
RvalidKnown_A	500805252	500698652	0	0
WreadyKnown_A	500805252	500698652	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	59951783	0	0
T1	42263	3485	0	0
T2	64373	6746	0	0
T3	57555	5254	0	0
T4	82756	8554	0	0
T5	82958	8367	0	0
T6	116647	77088	0	0
T8	82207	9130	0	0
T9	110991	12291	0	0
T31	76741	9081	0	0
T100	93929	11381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500805252	45037116	0	0
DepthKnown_A	500805252	500698652	0	0
RvalidKnown_A	500805252	500698652	0	0
WreadyKnown_A	500805252	500698652	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	45037116	0	0
T1	42263	1880	0	0
T2	64373	4634	0	0
T3	57555	3586	0	0
T4	82756	6886	0	0
T5	82958	5426	0	0
T6	116647	38144	0	0
T8	82207	6630	0	0
T9	110991	9735	0	0
T31	76741	6288	0	0
T100	93929	8827	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500805252	42098766	0	0
DepthKnown_A	500805252	500698652	0	0
RvalidKnown_A	500805252	500698652	0	0
WreadyKnown_A	500805252	500698652	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	42098766	0	0
T1	42263	461	0	0
T2	64373	3411	0	0
T3	57555	2972	0	0
T4	82756	5372	0	0
T5	82958	3862	0	0
T6	116647	7586	0	0
T8	82207	3933	0	0
T9	110991	9600	0	0
T31	76741	4486	0	0
T100	93929	7544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T39 T95 T96 
49         1/1              assign full_o = rready_i;
           Tests:       T39 T95 T96 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500805252	34758500	0	0
DepthKnown_A	500805252	500698652	0	0
RvalidKnown_A	500805252	500698652	0	0
WreadyKnown_A	500805252	500698652	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	34758500	0	0
T1	42263	353	0	0
T2	64373	3284	0	0
T3	57555	2859	0	0
T4	82756	5259	0	0
T5	82958	3673	0	0
T6	116647	6925	0	0
T8	82207	3797	0	0
T9	110991	9145	0	0
T31	76741	4315	0	0
T100	93929	7366	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500805252	500698652	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577241784	90319	0	0
DepthKnown_A	577241784	577119218	0	0
RvalidKnown_A	577241784	577119218	0	0
WreadyKnown_A	577241784	577119218	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	90319	0	0
T1	42263	8	0	0
T2	64373	13	0	0
T3	57555	13	0	0
T4	82756	13	0	0
T5	82958	27	0	0
T6	116647	34	0	0
T8	82207	13	0	0
T9	110991	208	0	0
T31	76741	18	0	0
T100	93929	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577241784	92880	0	0
DepthKnown_A	577241784	577119218	0	0
RvalidKnown_A	577241784	577119218	0	0
WreadyKnown_A	577241784	577119218	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	92880	0	0
T1	42263	8	0	0
T2	64373	13	0	0
T3	57555	13	0	0
T4	82756	13	0	0
T5	82958	27	0	0
T6	116647	34	0	0
T8	82207	13	0	0
T9	110991	208	0	0
T31	76741	18	0	0
T100	93929	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577241784	51994	0	0
DepthKnown_A	577241784	577119218	0	0
RvalidKnown_A	577241784	577119218	0	0
WreadyKnown_A	577241784	577119218	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	51994	0	0
T1	42263	8	0	0
T2	64373	12	0	0
T3	57555	12	0	0
T4	82756	12	0	0
T5	82958	24	0	0
T6	116647	31	0	0
T8	82207	12	0	0
T9	110991	205	0	0
T31	76741	15	0	0
T100	93929	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577241784	51993	0	0
DepthKnown_A	577241784	577119218	0	0
RvalidKnown_A	577241784	577119218	0	0
WreadyKnown_A	577241784	577119218	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	51993	0	0
T1	42263	8	0	0
T2	64373	12	0	0
T3	57555	12	0	0
T4	82756	12	0	0
T5	82958	24	0	0
T6	116647	31	0	0
T8	82207	12	0	0
T9	110991	205	0	0
T31	76741	15	0	0
T100	93929	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577241784	38325	0	0
DepthKnown_A	577241784	577119218	0	0
RvalidKnown_A	577241784	577119218	0	0
WreadyKnown_A	577241784	577119218	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	38325	0	0
T2	64373	1	0	0
T3	57555	1	0	0
T4	82756	1	0	0
T5	82958	3	0	0
T6	116647	3	0	0
T7	109585	3	0	0
T8	82207	1	0	0
T9	110991	3	0	0
T31	76741	3	0	0
T100	93929	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577241784	40887	0	0
DepthKnown_A	577241784	577119218	0	0
RvalidKnown_A	577241784	577119218	0	0
WreadyKnown_A	577241784	577119218	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	40887	0	0
T2	64373	1	0	0
T3	57555	1	0	0
T4	82756	1	0	0
T5	82958	3	0	0
T6	116647	3	0	0
T7	109585	3	0	0
T8	82207	1	0	0
T9	110991	3	0	0
T31	76741	3	0	0
T100	93929	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577241784	577119218	0	0
T1	42263	42201	0	0
T2	64373	64318	0	0
T3	57555	57497	0	0
T4	82756	82701	0	0
T5	82958	82896	0	0
T6	116647	116592	0	0
T8	82207	82149	0	0
T9	110991	110929	0	0
T31	76741	76679	0	0
T100	93929	93871	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0