Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_151.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T315 T319 T320
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_152.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T315 T319 T320
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_153.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T7 T14 T324
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_154.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T66 T315 T225
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_155.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T133 T306 T134
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_156.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T37 T281 T148
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T255 T256 T257
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_158.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T172 T120 T326
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_159.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T120 T180 T181
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_160.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T6 T316 T139
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_161.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T6 T316 T139
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_162.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T316 T139 T306
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_163.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T316 T139 T306
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;