Unified Coverage Report :: Module :: pinmux_strap_sampling

Module : pinmux_strap_sampling

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	99.34	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling	99.83	99.34	100.00			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	99.34	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.82	99.62	95.65			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.45	99.03	79.24	98.84		73.14	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pinmux_jtag_buf_dft	100.00	100.00
u_pinmux_jtag_buf_lc	100.00	100.00
u_pinmux_jtag_buf_rv	100.00	100.00
u_por_scanmode_sync	100.00						100.00
u_prim_lc_or_hardened	100.00	100.00	100.00				100.00
u_prim_lc_sender_pinmux_hw_debug_en	100.00	100.00				100.00
u_prim_lc_sync_lc_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_hw_debug_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_pinmux_hw_debug_en	100.00	100.00					100.00
u_rst_por_aon_n_mux	85.19	100.00	55.56				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pinmux_strap_sampling

	Line No.	Total	Covered	Percent
TOTAL		303	301	99.34
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ALWAYS	262	9	9	100.00
ALWAYS	283	9	9	100.00
CONT_ASSIGN	308	1	1	100.00
ALWAYS	312	17	17	100.00
CONT_ASSIGN	371	1	1	100.00
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CONT_ASSIGN	396	1	1	100.00
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131                       lc_tx_t lc_strap_en, lc_hw_debug_en_masked;
132        1/1            assign lc_strap_en = lc_tx_bool_to_lc_tx(strap_en_i);
           Tests:       T1 T2 T3 
133        1/1            assign lc_hw_debug_en_masked = lc_tx_and_hi(lc_strap_en, lc_hw_debug_en[0]);
           Tests:       T1 T2 T3 
134                     
135                       // Output ON if
136                       // - If the strap sampling pulse is asserted and lc_hw_debug_en is ON
137                       // - If the pinmux_hw_debug_en_q is already set to ON (this is the latching feedback loop)
138                       // Note: make sure we use a hardened, rectifying OR function since otherwise two non-strict
139                       // values may produce a strict ON value.
140                       lc_tx_t hw_debug_en_set, pinmux_hw_debug_en_q;
141                       prim_lc_or_hardened #(
142                         .ActVal(On)
143                       ) u_prim_lc_or_hardened (
144                         .clk_i,
145                         .rst_ni,
146                         .lc_en_a_i(lc_hw_debug_en_masked),
147                         .lc_en_b_i(pinmux_hw_debug_en_q),
148                         .lc_en_o  (hw_debug_en_set)
149                       );
150                     
151                       // Output ON if both lc_check_byp_en and lc_escalate_en are set to OFF.
152                       lc_tx_t hw_debug_en_gating;
153        1/1            assign hw_debug_en_gating = lc_tx_inv(lc_tx_and_lo(lc_check_byp_en[0], lc_escalate_en[0]));
           Tests:       T45 T36 T41 
154                     
155                       // Gate the hw_debug_en_set signal and feed it into the latching flop.
156                       lc_tx_t pinmux_hw_debug_en_d;
157        1/1            assign pinmux_hw_debug_en_d = lc_tx_and_hi(hw_debug_en_set, hw_debug_en_gating);
           Tests:       T1 T2 T3 
158                     
159                       prim_lc_sender u_prim_lc_sender_pinmux_hw_debug_en (
160                         .clk_i,
161                         .rst_ni,
162                         .lc_en_i(pinmux_hw_debug_en_d),
163                         .lc_en_o(pinmux_hw_debug_en_q)
164                       );
165                     
166                       typedef enum logic [1:0] {
167                         HwDebugEnSample,
168                         HwDebugEnTapSel,
169                         HwDebugEnRvDmOut,
170                         HwDebugEnLast
171                       } pinmux_hw_debug_en_e;
172                     
173                       lc_tx_t [HwDebugEnLast-1:0] pinmux_hw_debug_en;
174                       prim_lc_sync #(
175                         .NumCopies(int'(HwDebugEnLast)),
176                         .AsyncOn(0) // no sync needed
177                       ) u_prim_lc_sync_pinmux_hw_debug_en (
178                         .clk_i,
179                         .rst_ni,
180                         .lc_en_i(pinmux_hw_debug_en_q),
181                         .lc_en_o(pinmux_hw_debug_en)
182                       );
183                     
184                       // SEC_CM: PINMUX_HW_DEBUG_EN.INTERSIG.MUBI
185                       // We send this latched version over to the RV_DM in order to gate the JTAG signals and TAP side.
186                       // Note that the bus side will remain gated with the live lc_hw_debug_en value inside RV_DM.
187        1/1            assign pinmux_hw_debug_en_o = pinmux_hw_debug_en[HwDebugEnRvDmOut];
           Tests:       T1 T2 T3 
188                     
189                       // Check that we can correctly latch upon strap_en_i
190                       `ASSERT(LcHwDebugEnSet_A,
191                           (lc_tx_test_true_strict(lc_hw_debug_en[0]) ||
192                            lc_tx_test_true_strict(pinmux_hw_debug_en_q)) &&
193                           lc_tx_test_false_strict(lc_check_byp_en[0]) &&
194                           lc_tx_test_false_strict(lc_escalate_en[0]) &&
195                           strap_en_i
196                           |=>
197                           lc_tx_test_true_strict(pinmux_hw_debug_en_q))
198                       // Check that latching ON can only occur if lc_hw_debug_en_i is set.
199                       `ASSERT(LcHwDebugEnSetRev0_A,
200                           lc_tx_test_false_loose(pinmux_hw_debug_en_q) ##1
201                           lc_tx_test_true_strict(pinmux_hw_debug_en_q)
202                           |->
203                           $past(lc_tx_test_true_strict(lc_hw_debug_en[0])))
204                       // Check that latching ON can only occur if strap_en_i is set.
205                       `ASSERT(LcHwDebugEnSetRev1_A,
206                           lc_tx_test_false_loose(pinmux_hw_debug_en_q) ##1
207                           lc_tx_test_true_strict(pinmux_hw_debug_en_q)
208                           |->
209                           $past(strap_en_i))
210                       // Check that any non-OFF value on lc_check_byp_en_i and
211                       // lc_escalate_en_i clears the latched value.
212                       `ASSERT(LcHwDebugEnClear_A,
213                           lc_tx_test_true_loose(lc_check_byp_en[0]) ||
214                           lc_tx_test_true_loose(lc_escalate_en[0])
215                           |=>
216                           lc_tx_test_false_loose(pinmux_hw_debug_en_q))
217                     
218                       //////////////////////////
219                       // Strap Sampling Logic //
220                       //////////////////////////
221                     
222                       logic dft_strap_valid_d, dft_strap_valid_q;
223                       logic lc_strap_sample_en, rv_strap_sample_en, dft_strap_sample_en;
224                       logic [NTapStraps-1:0] tap_strap_d, tap_strap_q;
225                       logic [NDFTStraps-1:0] dft_strap_d, dft_strap_q;
226                     
227                       // SEC_CM: TAP.MUX.LC_GATED
228                       // The LC strap at index 0 has a slightly different
229                       // enable condition than the DFT strap at index 1.
230        1/1            assign tap_strap_d[0] = (lc_strap_sample_en) ? in_padring_i[TargetCfg.tap_strap0_idx] :
           Tests:       T1 T2 T3 
231                                                                      tap_strap_q[0];
232        1/1            assign tap_strap_d[1] = (rv_strap_sample_en) ? in_padring_i[TargetCfg.tap_strap1_idx] :
           Tests:       T1 T2 T3 
233                                                                      tap_strap_q[1];
234                     
235                       // We're always using the DFT strap sample enable for the DFT straps.
236        1/1            assign dft_strap_d = (dft_strap_sample_en) ? {in_padring_i[TargetCfg.dft_strap1_idx],
           Tests:       T1 T2 T3 
237                                                                     in_padring_i[TargetCfg.dft_strap0_idx]} :
238                                                                    dft_strap_q;
239                     
240        1/1            assign dft_strap_valid_d = dft_strap_sample_en | dft_strap_valid_q;
           Tests:       T1 T2 T3 
241        1/1            assign dft_strap_test_o.valid  = dft_strap_valid_q;
           Tests:       T1 T2 T3 
242        1/1            assign dft_strap_test_o.straps = dft_strap_q;
           Tests:       T85 T82 T83 
243                     
244                     
245                       // During dft enabled states, we continously sample all straps unless
246                       // told not to do so by external dft logic
247                       logic tap_sampling_en;
248                       logic dft_hold_tap_sel;
249                       // Delay the strap sampling pulse by one cycle so that the pinmux_hw_debug_en above can
250                       // propagate through the pinmux_hw_debug_en_q flop.
251                       logic strap_en_q;
252                     
253                       prim_buf #(
254                         .Width(1)
255                       ) u_buf_hold_tap (
256                         .in_i(dft_hold_tap_sel_i),
257                         .out_o(dft_hold_tap_sel)
258                       );
259        1/1            assign tap_sampling_en = lc_tx_test_true_strict(lc_dft_en[DftEnSample]) & ~dft_hold_tap_sel;
           Tests:       T1 T2 T3 
260                     
261                       always_comb begin : p_strap_sampling
262        1/1              lc_strap_sample_en = 1'b0;
           Tests:       T1 T2 T3 
263        1/1              rv_strap_sample_en = 1'b0;
           Tests:       T1 T2 T3 
264        1/1              dft_strap_sample_en = 1'b0;
           Tests:       T1 T2 T3 
265                         // Initial strap sampling pulse from pwrmgr,
266                         // qualified by life cycle signals.
267                         // The DFT-mode straps are always sampled only once.
268        1/1              if (strap_en_q && tap_sampling_en) begin
           Tests:       T1 T2 T3 
269        1/1                dft_strap_sample_en = 1'b1;
           Tests:       T1 T2 T3 
270                         end
                        MISSING_ELSE
271                         // In DFT-enabled life cycle states we continously
272                         // sample the TAP straps to be able to switch back and
273                         // forth between different TAPs.
274        1/1              if (strap_en_q || tap_sampling_en) begin
           Tests:       T1 T2 T3 
275        1/1                lc_strap_sample_en = 1'b1;
           Tests:       T1 T2 T3 
276        1/1                if (lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnSample])) begin
           Tests:       T1 T2 T3 
277        1/1                  rv_strap_sample_en = 1'b1;
           Tests:       T1 T2 T3 
278                           end
                        MISSING_ELSE
279                         end
                        MISSING_ELSE
280                       end
281                     
282                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_strap_sample
283        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
284        1/1                tap_strap_q         <= '0;
           Tests:       T1 T2 T3 
285        1/1                dft_strap_q         <= '0;
           Tests:       T1 T2 T3 
286        1/1                dft_strap_valid_q   <= 1'b0;
           Tests:       T1 T2 T3 
287        1/1                strap_en_q          <= 1'b0;
           Tests:       T1 T2 T3 
288                         end else begin
289        1/1                tap_strap_q         <= tap_strap_d;
           Tests:       T1 T2 T3 
290        1/1                dft_strap_q         <= dft_strap_d;
           Tests:       T1 T2 T3 
291        1/1                dft_strap_valid_q   <= dft_strap_valid_d;
           Tests:       T1 T2 T3 
292        1/1                strap_en_q          <= strap_en_i;
           Tests:       T1 T2 T3 
293                         end
294                       end
295                     
296                       ///////////////////////
297                       // TAP Selection Mux //
298                       ///////////////////////
299                     
300                       logic jtag_en;
301                       tap_strap_t tap_strap;
302                       jtag_pkg::jtag_req_t jtag_req, lc_jtag_req, rv_jtag_req, dft_jtag_req;
303                       jtag_pkg::jtag_rsp_t jtag_rsp, lc_jtag_rsp, rv_jtag_rsp, dft_jtag_rsp;
304                     
305                       // This muxes the JTAG signals to the correct TAP, based on the
306                       // sampled straps. Further, the individual JTAG signals are gated
307                       // using the corresponding life cycle signal.
308        1/1            assign tap_strap = tap_strap_t'(tap_strap_q);
           Tests:       T38 T36 T41 
309                       `ASSERT_KNOWN(TapStrapKnown_A, tap_strap)
310                     
311                       always_comb begin : p_tap_mux
312        1/1              jtag_rsp     = '0;
           Tests:       T1 T2 T3 
313                         // Note that this holds the JTAGs in reset
314                         // when they are not selected.
315        1/1              lc_jtag_req  = '0;
           Tests:       T1 T2 T3 
316        1/1              rv_jtag_req  = '0;
           Tests:       T1 T2 T3 
317        1/1              dft_jtag_req = '0;
           Tests:       T1 T2 T3 
318                         // This activates the TDO override further below.
319        1/1              jtag_en      = 1'b0;
           Tests:       T1 T2 T3 
320                     
321        1/1              unique case (tap_strap)
           Tests:       T1 T2 T3 
322                           LcTapSel: begin
323        1/1                  lc_jtag_req = jtag_req;
           Tests:       T38 T36 T41 
324        1/1                  jtag_rsp    = lc_jtag_rsp;
           Tests:       T38 T36 T41 
325        1/1                  jtag_en     = 1'b1;
           Tests:       T38 T36 T41 
326                           end
327                           RvTapSel: begin
328        1/1                  if (lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnTapSel])) begin
           Tests:       T85 T86 T87 
329        1/1                    rv_jtag_req = jtag_req;
           Tests:       T85 T86 T87 
330        1/1                    jtag_rsp    = rv_jtag_rsp;
           Tests:       T85 T86 T87 
331        1/1                    jtag_en     = 1'b1;
           Tests:       T85 T86 T87 
332                             end
                        MISSING_ELSE
333                           end
334                           DftTapSel: begin
335        1/1                  if (lc_tx_test_true_strict(lc_dft_en[DftEnTapSel])) begin
           Tests:       T82 T83 T84 
336        1/1                    dft_jtag_req = jtag_req;
           Tests:       T82 T83 T84 
337        1/1                    jtag_rsp     = dft_jtag_rsp;
           Tests:       T82 T83 T84 
338        1/1                    jtag_en      = 1'b1;
           Tests:       T82 T83 T84 
339                             end
                        MISSING_ELSE
340                           end
341                           default: ;
342                         endcase // tap_strap_t'(tap_strap_q)
343                       end
344                     
345                       // Insert hand instantiated buffers for
346                       // these signals to prevent further optimization.
347                       pinmux_jtag_buf u_pinmux_jtag_buf_lc (
348                         .req_i(lc_jtag_req),
349                         .req_o(lc_jtag_o),
350                         .rsp_i(lc_jtag_i),
351                         .rsp_o(lc_jtag_rsp)
352                       );
353                       pinmux_jtag_buf u_pinmux_jtag_buf_rv (
354                         .req_i(rv_jtag_req),
355                         .req_o(rv_jtag_o),
356                         .rsp_i(rv_jtag_i),
357                         .rsp_o(rv_jtag_rsp)
358                       );
359                       pinmux_jtag_buf u_pinmux_jtag_buf_dft (
360                         .req_i(dft_jtag_req),
361                         .req_o(dft_jtag_o),
362                         .rsp_i(dft_jtag_i),
363                         .rsp_o(dft_jtag_rsp)
364                       );
365                     
366                       //////////////////////
367                       // TAP Input Muxes  //
368                       //////////////////////
369                     
370                       // Inputs connections
371        1/1            assign jtag_req.tck    = in_padring_i[TargetCfg.tck_idx];
           Tests:       T9 T32 T38 
372        1/1            assign jtag_req.tms    = in_padring_i[TargetCfg.tms_idx];
           Tests:       T9 T32 T38 
373        1/1            assign jtag_req.tdi    = in_padring_i[TargetCfg.tdi_idx];
           Tests:       T9 T32 T27 
374                     
375                       // Note that this resets the selected TAP controller in
376                       // scanmode. If the TAP controller needs to be active during
377                       // reset, this reset bypass needs to be adapted accordingly.
378                       prim_clock_mux2 #(
379                         .NoFpgaBufG(1'b1)
380                       ) u_rst_por_aon_n_mux (
381                         .clk0_i(in_padring_i[TargetCfg.trst_idx]),
382                         .clk1_i(rst_ni),
383                         .sel_i(prim_mubi_pkg::mubi4_test_true_strict(scanmode[0])),
384                         .clk_o(jtag_req.trst_n)
385                       );
386                     
387                       // Input tie-off muxes and output overrides
388                       for (genvar k = 0; k < NumIOs; k++) begin : gen_input_tie_off
389                         if (k == TargetCfg.tck_idx  ||
390                             k == TargetCfg.tms_idx  ||
391                             k == TargetCfg.trst_idx ||
392                             k == TargetCfg.tdi_idx  ||
393                             k == TargetCfg.tdo_idx) begin : gen_jtag_signal
394                     
395                           // Tie off inputs.
396        5/5                assign in_core_o[k] = (jtag_en) ? 1'b0 : in_padring_i[k];
           Tests:       T9 T32 T38  | T9 T32 T38  | T9 T32 T27  | T9 T32 T38  | T9 T32 T38 
397                     
398                           if (k == TargetCfg.tdo_idx) begin : gen_output_mux
399                             // Override TDO output.
400        1/1                  assign out_padring_o[k] = (jtag_en) ? jtag_rsp.tdo    : out_core_i[k];
           Tests:       T32 T38 T36 
401        1/1                  assign oe_padring_o[k]  = (jtag_en) ? jtag_rsp.tdo_oe : oe_core_i[k];
           Tests:       T32 T38 T36 
402                           end else begin : gen_output_tie_off
403                             // Make sure these pads are set to high-z.
404        4/4                  assign out_padring_o[k] = (jtag_en) ? 1'b0 : out_core_i[k];
           Tests:       T32 T38 T36  | T9 T32 T38  | T9 T32 T38  | T9 T32 T38 
405        4/4                  assign oe_padring_o[k]  = (jtag_en) ? 1'b0 : oe_core_i[k];
           Tests:       T32 T38 T36  | T9 T32 T38  | T9 T32 T38  | T9 T32 T38 
406                           end
407                     
408                           // Also reset all corresponding pad attributes to the default ('0) when JTAG is enabled.
409                           // This disables functional pad features that may have been set, e.g., pull-up/pull-down.
410                           // Do enable schmitt trigger on JTAG clock and JTAG reset for better signal integrity.
411                           if (k == TargetCfg.tck_idx  || k == TargetCfg.trst_idx) begin : gen_schmitt_en
412        2/2                  assign attr_padring_o[k] = (jtag_en) ? '{schmitt_en: 1'b1, default: '0} : attr_core_i[k];
           Tests:       T38 T36 T41  | T38 T36 T41 
413                           end else begin : gen_no_schmitt
414        3/3                  assign attr_padring_o[k] = (jtag_en) ? '0 : attr_core_i[k];
           Tests:       T38 T36 T41  | T38 T36 T41  | T38 T36 T41 
415                           end
416                         end else begin : gen_other_inputs
417        58/58              assign attr_padring_o[k] = attr_core_i[k];
           Tests:       T25 T24 T26  | T25 T24 T26  | T31 T47 T48  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T15 T51 T52  | T25 T24 T26  | T31 T47 T48  | T31 T11 T12  | T25 T24 T26  | T31 T11 T12  | T31 T13 T47  | T31 T13 T47  | T31 T13 T47  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T56 T53 T54  | T56 T53 T54  | T56 T53 T54  | T1 T2 T3  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T1 T2 T3  | T1 T2 T3  | T31 T11 T12  | T31 T11 T12  | T31 T11 T12  | T31 T11 T12  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T25 T24 T26  | T19 T49 T50  | T19 T49 T50  | T25 T24 T26  | T25 T24 T26  | T31 T47 T48  | T31 T47 T48 
418        58/58              assign in_core_o[k]      = in_padring_i[k];
           Tests:       T9 T7 T30  | T9 T7 T30  | T9 T31 T7  | T9 T7 T32  | T9 T7 T32  | T9 T7 T32  | T9 T7 T32  | T9 T7 T14  | T9 T7 T14  | T9 T31 T39  | T9 T31 T11  | T9 T14 T39  | T9 T31 T11  | T9 T31 T14  | T1 T2 T3  | T9 T31 T32  | T9 T32 T16  | T9 T32 T33  | T9 T5 T32  | T9 T5 T32  | T9 T5 T34  | T9 T5 T34  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T9 T35 T36  | T2 T8 T9  | T1 T2 T3  | T9 T32 T33  | T9 T32 T37  | T9 T32 T37  | T9 T32 T37  | T1 T2 T3  | T9 T32 T16  | T1 T2 T3  | T9 T32 T39  | T9 T32 T39  | T9 T32 T39  | T9 T32 T33  | T2 T8 T9  | T8 T9 T10  | T9 T31 T11  | T9 T31 T11  | T9 T31 T11  | T9 T31 T11  | T9 T14 T15  | T9 T14 T15  | T9 T14 T15  | T9 T14 T15  | T9 T27 T33  | T27 T33 T16  | T9 T14 T15  | T9 T14 T27  | T9 T31 T11  | T9 T31 T14 
419        56/58   ==>        assign out_padring_o[k]  = out_core_i[k];
           Tests:       T7 T32 T42  | T7 T30 T32  | T7 T32 T122  | T7 T32 T42  | T9 T7 T32  | T7 T32 T35  | T7 T32 T42  | T9 T7 T32  | T32 T42 T23  | T31 T11 T12  | T31 T13 T47  | T9 T13 T67  | T9 T31 T47  | T9 T13 T29  | T1 T2 T3  | T32 T13 T42  | T9 T32 T16  | T9 T32 T13  | T9 T5 T32  | T5 T32 T37  | T9 T5 T32  | T5 T32 T37  | T23 T25 T24  | T9 T29 T25  | T29 T25 T24  | T25 T24 T26  | T1 T2 T3  | T29 T25 T24  | T29 T25 T24  | T9 T16 T18  | T23 T29 T25  | T9 T32 T16  | T32 T37 T122  | T9 T32 T37  | T9 T32 T37  | T9 T32 T16  | T9 T32 T16  | T32 T13 T42  | T32 T13 T42  | T32 T13 T42  | T9 T32 T42  | T32 T13 T42  | T8 T9 T10  | T8 T9 T10  | T11 T12 T13  | T11 T12 T13  | T9 T11 T12  | T9 T11 T12  | T9 T14 T11  | T14 T15 T11  | T9 T14 T11  | T9 T14 T11  | T16 T17 T18  | T16 T19 T17  | T11 T12 T13  | T9 T11 T12 
420        58/58              assign oe_padring_o[k]   = oe_core_i[k];
           Tests:       T7 T32 T42  | T7 T30 T32  | T9 T7 T32  | T9 T7 T32  | T9 T7 T32  | T7 T32 T35  | T9 T7 T32  | T9 T7 T14  | T9 T32 T58  | T31 T13 T23  | T31 T13 T23  | T9 T13 T67  | T9 T31 T13  | T9 T13 T29  | T1 T2 T3  | T32 T13 T42  | T9 T32 T16  | T9 T32 T13  | T9 T5 T32  | T5 T32 T60  | T9 T5 T32  | T9 T5 T34  | T9 T23 T25  | T9 T23 T29  | T29 T25 T24  | T25 T24 T26  | T1 T2 T3  | T23 T29 T25  | T23 T29 T25  | T9 T16 T18  | T23 T29 T25  | T9 T32 T16  | T9 T32 T37  | T9 T32 T37  | T9 T32 T37  | T9 T32 T16  | T9 T32 T16  | T32 T13 T42  | T32 T13 T42  | T32 T13 T42  | T9 T32 T42  | T32 T13 T42  | T20 T21 T22  | T9 T20 T21  | T9 T11 T12  | T9 T23 T24  | T9 T23 T29  | T9 T23 T29  | T9 T14 T11  | T14 T15 T11  | T9 T14 T11  | T9 T14 T11  | T9 T27 T28  | T27 T28 T29  | T25 T24 T26  | T25 T24 T26  | T9 T11 T12  | T11 T12 T13 

---

Cond Coverage for Module : pinmux_strap_sampling

	Total	Covered	Percent
Conditions	55	55	100.00
Logical	55	55	100.00
Non-Logical	0	0
Event	0	0

 LINE       230
 EXPRESSION (lc_strap_sample_en ? in_padring_i[30] : tap_strap_q[0])
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       232
 EXPRESSION (rv_strap_sample_en ? in_padring_i[27] : tap_strap_q[1])
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (dft_strap_sample_en ? ({in_padring_i[42], in_padring_i[40]}) : dft_strap_q)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       240
 EXPRESSION (dft_strap_sample_en | dft_strap_valid_q)
             ---------1---------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       268
 EXPRESSION (strap_en_q && tap_sampling_en)
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T27,T40
1	1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (strap_en_q || tap_sampling_en)
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T9,T45,T27
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T27,T40

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       400
 EXPRESSION (jtag_en ? jtag_rsp.tdo : out_core_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       401
 EXPRESSION (jtag_en ? jtag_rsp.tdo_oe : oe_core_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       412
 EXPRESSION 
 Number  Term
      1  jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[38])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       412
 EXPRESSION 
 Number  Term
      1  jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[39])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       414
 EXPRESSION (jtag_en ? '0 : attr_core_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       414
 EXPRESSION (jtag_en ? '0 : attr_core_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

 LINE       414
 EXPRESSION (jtag_en ? '0 : attr_core_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T36,T41

---

Branch Coverage for Module : pinmux_strap_sampling

	Line No.	Total	Covered	Percent
Branches		59	59	100.00
TERNARY	230	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	405	2	2	100.00
TERNARY	414	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	400	2	2	100.00
TERNARY	401	2	2	100.00
TERNARY	414	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	405	2	2	100.00
TERNARY	414	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	405	2	2	100.00
TERNARY	412	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	405	2	2	100.00
TERNARY	412	2	2	100.00
IF	268	2	2	100.00
IF	274	3	3	100.00
IF	283	2	2	100.00
CASE	321	6	6	100.00

230          assign tap_strap_d[0] = (lc_strap_sample_en) ? in_padring_i[TargetCfg.tap_strap0_idx] :
                                                          -1-  
                                                          ==>  
                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

232          assign tap_strap_d[1] = (rv_strap_sample_en) ? in_padring_i[TargetCfg.tap_strap1_idx] :
                                                          -1-  
                                                          ==>  
                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

236          assign dft_strap_d = (dft_strap_sample_en) ? {in_padring_i[TargetCfg.dft_strap1_idx],
                                                        -1-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

396              assign in_core_o[k] = (jtag_en) ? 1'b0 : in_padring_i[k];
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

404                assign out_padring_o[k] = (jtag_en) ? 1'b0 : out_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

405                assign oe_padring_o[k]  = (jtag_en) ? 1'b0 : oe_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

414                assign attr_padring_o[k] = (jtag_en) ? '0 : attr_core_i[k];
                                                        -1-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

396              assign in_core_o[k] = (jtag_en) ? 1'b0 : in_padring_i[k];
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

400                assign out_padring_o[k] = (jtag_en) ? jtag_rsp.tdo    : out_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

401                assign oe_padring_o[k]  = (jtag_en) ? jtag_rsp.tdo_oe : oe_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

414                assign attr_padring_o[k] = (jtag_en) ? '0 : attr_core_i[k];
                                                        -1-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

396              assign in_core_o[k] = (jtag_en) ? 1'b0 : in_padring_i[k];
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

404                assign out_padring_o[k] = (jtag_en) ? 1'b0 : out_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

405                assign oe_padring_o[k]  = (jtag_en) ? 1'b0 : oe_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

414                assign attr_padring_o[k] = (jtag_en) ? '0 : attr_core_i[k];
                                                        -1-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

396              assign in_core_o[k] = (jtag_en) ? 1'b0 : in_padring_i[k];
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

404                assign out_padring_o[k] = (jtag_en) ? 1'b0 : out_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

405                assign oe_padring_o[k]  = (jtag_en) ? 1'b0 : oe_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

412                assign attr_padring_o[k] = (jtag_en) ? '{schmitt_en: 1'b1, default: '0} : attr_core_i[k];
                                                        -1-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

396              assign in_core_o[k] = (jtag_en) ? 1'b0 : in_padring_i[k];
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

404                assign out_padring_o[k] = (jtag_en) ? 1'b0 : out_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

405                assign oe_padring_o[k]  = (jtag_en) ? 1'b0 : oe_core_i[k];
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

412                assign attr_padring_o[k] = (jtag_en) ? '{schmitt_en: 1'b1, default: '0} : attr_core_i[k];
                                                        -1-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T36,T41
0	Covered	T1,T2,T3

268            if (strap_en_q && tap_sampling_en) begin
               -1-  
269              dft_strap_sample_en = 1'b1;
                 ==>
270            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

274            if (strap_en_q || tap_sampling_en) begin
               -1-  
275              lc_strap_sample_en = 1'b1;
276              if (lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnSample])) begin
                 -2-  
277                rv_strap_sample_en = 1'b1;
                   ==>
278              end
                 MISSING_ELSE
                 ==>
279            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T9,T45,T27

283            if (!rst_ni) begin
               -1-  
284              tap_strap_q         <= '0;
                 ==>
285              dft_strap_q         <= '0;
286              dft_strap_valid_q   <= 1'b0;
287              strap_en_q          <= 1'b0;
288            end else begin
289              tap_strap_q         <= tap_strap_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

321            unique case (tap_strap)
                      -1-  
322              LcTapSel: begin
323                lc_jtag_req = jtag_req;
                   ==>
324                jtag_rsp    = lc_jtag_rsp;
325                jtag_en     = 1'b1;
326              end
327              RvTapSel: begin
328                if (lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnTapSel])) begin
                   -2-  
329                  rv_jtag_req = jtag_req;
                     ==>
330                  jtag_rsp    = rv_jtag_rsp;
331                  jtag_en     = 1'b1;
332                end
                   MISSING_ELSE
                   ==>
333              end
334              DftTapSel: begin
335                if (lc_tx_test_true_strict(lc_dft_en[DftEnTapSel])) begin
                   -3-  
336                  dft_jtag_req = jtag_req;
                     ==>
337                  jtag_rsp     = dft_jtag_rsp;
338                  jtag_en      = 1'b1;
339                end
                   MISSING_ELSE
                   ==>
340              end
341              default: ;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
LcTapSel	-	-	Covered	T38,T36,T41
RvTapSel	1	-	Covered	T85,T86,T87
RvTapSel	0	-	Covered	T89,T625,T626
DftTapSel	-	1	Covered	T82,T83,T84
DftTapSel	-	0	Covered	T627
default	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : pinmux_strap_sampling

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DftTapOff0_A	126339320	39008999	0	284
LcHwDebugEnClear_A	126339320	11961846	0	15
LcHwDebugEnSetRev0_A	126339320	1455	0	101
LcHwDebugEnSetRev1_A	126339320	1455	0	101
LcHwDebugEnSet_A	126339320	1455	0	0
RvTapOff0_A	126339320	262	0	202
RvTapOff1_A	126339320	35828112	0	0
TapStrapKnown_A	126339320	125649459	0	0
dft_strap0_idxRange_A	1022	1022	0	0
dft_strap1_idxRange_A	1022	1022	0	0
tap_strap0_idxRange_A	1022	1022	0	0
tap_strap1_idxRange_A	1022	1022	0	0
tck_idxRange_A	1022	1022	0	0
tdi_idxRange_A	1022	1022	0	0
tdo_idxRange_A	1022	1022	0	0
tms_idxRange_A	1022	1022	0	0
trst_idxRange_A	1022	1022	0	0

DftTapOff0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126339320	39008999	0	284
T1	11144	2484	0	0
T2	16115	2481	0	0
T3	14664	2483	0	0
T4	20845	2481	0	0
T5	20616	2483	0	0
T6	28773	2481	0	0
T8	21053	2483	0	0
T9	28136	27479	0	2
T27	0	0	0	2
T31	19148	2483	0	0
T36	0	0	0	2
T41	0	0	0	2
T57	0	0	0	2
T80	0	0	0	2
T100	23519	2483	0	0
T187	0	0	0	2
T192	0	0	0	2
T193	0	0	0	2
T199	0	0	0	2

LcHwDebugEnClear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126339320	11961846	0	15
T10	41656	0	0	0
T14	37340	0	0	0
T15	38374	0	0	0
T20	45302	0	0	0
T30	53960	0	0	0
T32	46690	0	0	0
T34	44255	0	0	0
T36	0	1865	0	1
T41	0	1473	0	1
T45	56465	5103	0	0
T57	0	2005	0	1
T79	0	5093	0	0
T80	0	1134	0	1
T81	0	4987	0	0
T113	41320	0	0	0
T114	55322	0	0	0
T187	0	491	0	1
T192	0	2021	0	0
T193	0	1641	0	1
T628	0	0	0	1
T629	0	0	0	1
T630	0	0	0	1
T631	0	0	0	1

LcHwDebugEnSetRev0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126339320	1455	0	101
T1	11144	1	0	0
T2	16115	1	0	0
T3	14664	1	0	0
T4	20845	1	0	0
T5	20616	1	0	0
T6	28773	1	0	0
T7	0	1	0	0
T8	21053	1	0	0
T9	28136	0	0	1
T27	0	0	0	1
T31	19148	1	0	0
T36	0	0	0	1
T41	0	0	0	1
T57	0	0	0	1
T80	0	0	0	1
T100	23519	1	0	0
T187	0	0	0	1
T188	0	0	0	1
T193	0	0	0	1
T199	0	0	0	1

LcHwDebugEnSetRev1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126339320	1455	0	101
T1	11144	1	0	0
T2	16115	1	0	0
T3	14664	1	0	0
T4	20845	1	0	0
T5	20616	1	0	0
T6	28773	1	0	0
T7	0	1	0	0
T8	21053	1	0	0
T9	28136	0	0	1
T27	0	0	0	1
T31	19148	1	0	0
T36	0	0	0	1
T41	0	0	0	1
T57	0	0	0	1
T80	0	0	0	1
T100	23519	1	0	0
T187	0	0	0	1
T188	0	0	0	1
T193	0	0	0	1
T199	0	0	0	1

LcHwDebugEnSet_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126339320	1455	0	0
T1	11144	1	0	0
T2	16115	1	0	0
T3	14664	1	0	0
T4	20845	1	0	0
T5	20616	1	0	0
T6	28773	1	0	0
T7	0	1	0	0
T8	21053	1	0	0
T9	28136	0	0	0
T31	19148	1	0	0
T100	23519	1	0	0

RvTapOff0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126339320	262	0	202
T5	20616	0	0	0
T6	28773	0	0	0
T7	38892	0	0	0
T9	28136	1	0	2
T10	41656	0	0	0
T14	37340	0	0	0
T27	0	1	0	2
T31	19148	0	0	0
T34	44255	0	0	0
T36	0	2	0	2
T40	0	1	0	0
T41	0	1	0	2
T45	56465	0	0	0
T57	0	2	0	2
T80	0	1	0	2
T113	41320	0	0	0
T187	0	1	0	2
T188	0	0	0	2
T192	0	1	0	0
T193	0	2	0	2
T199	0	0	0	2

RvTapOff1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126339320	35828112	0	0
T1	11144	3028	0	0
T2	16115	2667	0	0
T3	14664	2934	0	0
T4	20845	2844	0	0
T5	20616	2772	0	0
T6	28773	2776	0	0
T8	21053	3257	0	0
T9	28136	27481	0	0
T31	19148	2834	0	0
T100	23519	3052	0	0

TapStrapKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126339320	125649459	0	0
T1	11144	10510	0	0
T2	16115	15818	0	0
T3	14664	14181	0	0
T4	20845	20230	0	0
T5	20616	20277	0	0
T6	28773	28365	0	0
T8	21053	20098	0	0
T9	28136	27481	0	0
T31	19148	18785	0	0
T100	23519	22911	0	0

dft_strap0_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

dft_strap1_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

tap_strap0_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

tap_strap1_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

tck_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

tdi_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

tdo_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

tms_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0

trst_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T31	1	1	0	0
T100	1	1	0	0