Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_por_aon_n_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T14 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T14,T11
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T31,T14
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T14,T11

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	27792	27262	0	0
selKnown1	130726	129321	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	27792	27262	0	0
T11	238	237	0	0
T12	19	18	0	0
T13	1026	1025	0	0
T26	16	15	0	0
T32	4	3	0	0
T36	2	1	0	0
T38	1	0	0	0
T41	2	1	0	0
T46	7	6	0	0
T57	2	1	0	0
T80	1	0	0	0
T85	0	2	0	0
T88	0	1	0	0
T187	1	0	0	0
T188	3	2	0	0
T192	3	2	0	0
T193	2	1	0	0
T209	0	5	0	0
T210	252	251	0	0
T211	7	6	0	0
T212	5	4	0	0
T213	7	6	0	0
T214	10	9	0	0
T215	2	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	130726	129321	0	0
T10	1	0	0	0
T14	1	0	0	0
T15	1	0	0	0
T20	1	0	0	0
T24	13	19	0	0
T25	13	28	0	0
T26	12	24	0	0
T30	1	0	0	0
T31	545	544	0	0
T32	1	0	0	0
T34	1	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	2	1	0	0
T46	4	5	0	0
T57	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T113	1	0	0	0
T114	1	0	0	0
T182	0	1	0	0
T192	0	2	0	0
T193	0	1	0	0
T211	13	12	0	0
T212	9	8	0	0
T213	22	21	0	0
T214	16	15	0	0
T215	13	12	0	0
T216	9	8	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T32,T38,T36
0	1	Covered	T9,T32,T38
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T32,T38,T36
1	1	Covered	T9,T32,T38

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	878	745	0	0
selKnown1	1760	748	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	745	0	0
T32	4	3	0	0
T36	2	1	0	0
T38	1	0	0	0
T41	2	1	0	0
T57	2	1	0	0
T80	1	0	0	0
T85	0	2	0	0
T88	0	1	0	0
T187	1	0	0	0
T188	3	2	0	0
T192	3	2	0	0
T193	2	1	0	0
T209	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760	748	0	0
T10	1	0	0	0
T14	1	0	0	0
T15	1	0	0	0
T20	1	0	0	0
T30	1	0	0	0
T32	1	0	0	0
T34	1	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	2	1	0	0
T57	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T113	1	0	0	0
T114	1	0	0	0
T182	0	1	0	0
T192	0	2	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T13
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T31,T11,T12
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T13

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	3975	3954	0	0
selKnown1	3525	3501	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	3975	3954	0	0
T11	238	237	0	0
T12	19	18	0	0
T13	1026	1025	0	0
T25	0	6	0	0
T29	1	0	0	0
T67	1026	1025	0	0
T123	1026	1025	0	0
T210	252	251	0	0
T217	19	18	0	0
T218	19	18	0	0
T219	209	208	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	3525	3501	0	0
T11	1	0	0	0
T12	1	0	0	0
T13	576	575	0	0
T23	1	0	0	0
T24	0	7	0	0
T25	0	16	0	0
T26	0	13	0	0
T29	1	0	0	0
T31	545	544	0	0
T46	0	2	0	0
T47	545	544	0	0
T48	545	544	0	0
T67	0	575	0	0
T123	0	575	0	0
T210	1	0	0	0
T217	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T13 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T23,T29
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T31,T13,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T23,T29

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	58	47	0	0
selKnown1	132	114	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	58	47	0	0
T26	16	15	0	0
T46	7	6	0	0
T211	7	6	0	0
T212	5	4	0	0
T213	7	6	0	0
T214	10	9	0	0
T215	2	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	132	114	0	0
T24	13	12	0	0
T25	13	12	0	0
T26	12	11	0	0
T46	4	3	0	0
T211	13	12	0	0
T212	9	8	0	0
T213	22	21	0	0
T214	16	15	0	0
T215	13	12	0	0
T216	9	8	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T13
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T31,T13,T47
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T13

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	3957	3936	0	0
selKnown1	168	152	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	3957	3936	0	0
T11	241	240	0	0
T12	19	18	0	0
T13	1025	1024	0	0
T23	1	0	0	0
T25	0	6	0	0
T67	1026	1025	0	0
T123	1025	1024	0	0
T210	246	245	0	0
T217	19	18	0	0
T218	19	18	0	0
T219	195	194	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	168	152	0	0
T13	2	1	0	0
T24	13	12	0	0
T25	15	14	0	0
T26	20	19	0	0
T31	2	1	0	0
T46	4	3	0	0
T47	2	1	0	0
T48	2	1	0	0
T67	2	1	0	0
T123	2	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T13 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T23,T29
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T31,T13,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T23,T29

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	49	37	0	0
selKnown1	146	128	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	49	37	0	0
T26	9	8	0	0
T46	6	5	0	0
T211	5	4	0	0
T212	6	5	0	0
T213	3	2	0	0
T214	9	8	0	0
T215	2	1	0	0
T216	5	4	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	146	128	0	0
T24	14	13	0	0
T25	17	16	0	0
T26	15	14	0	0
T46	3	2	0	0
T211	21	20	0	0
T212	11	10	0	0
T213	22	21	0	0
T214	12	11	0	0
T215	7	6	0	0
T216	16	15	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T14 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T14,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T67
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T14,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4295	4272	0	0
selKnown1	477	463	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4295	4272	0	0
T11	350	349	0	0
T12	1	0	0	0
T13	1025	1024	0	0
T24	0	10	0	0
T25	0	6	0	0
T26	0	20	0	0
T46	0	17	0	0
T67	1025	1024	0	0
T77	1	0	0	0
T78	1	0	0	0
T123	0	1024	0	0
T210	368	367	0	0
T217	1	0	0	0
T218	1	0	0	0
T219	358	357	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	477	463	0	0
T13	117	116	0	0
T24	16	15	0	0
T25	12	11	0	0
T26	10	9	0	0
T46	3	2	0	0
T67	117	116	0	0
T123	117	116	0	0
T211	18	17	0	0
T212	14	13	0	0
T216	7	6	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T14 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T14,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T67
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T14,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	66	46	0	0
selKnown1	117	103	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	66	46	0	0
T11	3	2	0	0
T13	1	0	0	0
T24	5	4	0	0
T25	5	4	0	0
T26	0	7	0	0
T46	0	8	0	0
T67	1	0	0	0
T77	1	0	0	0
T78	1	0	0	0
T123	1	0	0	0
T210	3	2	0	0
T211	0	3	0	0
T213	0	3	0	0
T216	0	1	0	0
T219	3	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	117	103	0	0
T24	17	16	0	0
T25	10	9	0	0
T26	11	10	0	0
T46	5	4	0	0
T211	18	17	0	0
T212	8	7	0	0
T213	10	9	0	0
T214	19	18	0	0
T215	10	9	0	0
T216	5	4	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T14 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T14,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T31,T47
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T14,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4279	4256	0	0
selKnown1	562	548	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4279	4256	0	0
T11	352	351	0	0
T12	1	0	0	0
T13	1025	1024	0	0
T24	0	8	0	0
T25	0	6	0	0
T26	0	15	0	0
T46	0	25	0	0
T67	1026	1025	0	0
T77	1	0	0	0
T78	1	0	0	0
T123	0	1024	0	0
T210	362	361	0	0
T217	1	0	0	0
T218	1	0	0	0
T219	342	341	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	562	548	0	0
T24	12	11	0	0
T25	16	15	0	0
T26	10	9	0	0
T31	139	138	0	0
T46	6	5	0	0
T47	127	126	0	0
T48	147	146	0	0
T211	26	25	0	0
T212	14	13	0	0
T216	15	14	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T14 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T14,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T31,T13
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T14,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	72	50	0	0
selKnown1	144	127	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	72	50	0	0
T11	3	2	0	0
T13	1	0	0	0
T23	1	0	0	0
T24	0	5	0	0
T25	0	1	0	0
T26	0	10	0	0
T29	1	0	0	0
T46	0	9	0	0
T67	1	0	0	0
T77	1	0	0	0
T78	1	0	0	0
T123	1	0	0	0
T210	3	2	0	0
T211	0	6	0	0
T212	0	6	0	0
T216	0	2	0	0
T219	3	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	144	127	0	0
T24	11	10	0	0
T25	14	13	0	0
T26	21	20	0	0
T46	5	4	0	0
T211	18	17	0	0
T212	15	14	0	0
T213	25	24	0	0
T214	11	10	0	0
T215	7	6	0	0
T216	10	9	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T9,T31,T39
0	1	Covered	T9,T31,T13
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T31,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T9,T31,T39
1	1	Covered	T9,T31,T13

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	3574	3549	0	0
selKnown1	3808	3778	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	3574	3549	0	0
T13	576	575	0	0
T23	1	0	0	0
T24	0	14	0	0
T25	0	20	0	0
T26	0	6	0	0
T29	1	0	0	0
T31	546	545	0	0
T39	1	0	0	0
T46	0	14	0	0
T47	546	545	0	0
T48	546	545	0	0
T67	0	575	0	0
T95	1	0	0	0
T96	1	0	0	0
T123	0	575	0	0
T220	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	3808	3778	0	0
T11	202	201	0	0
T12	1	0	0	0
T13	1025	1024	0	0
T24	0	12	0	0
T25	0	5	0	0
T26	0	12	0	0
T39	1	0	0	0
T46	0	19	0	0
T47	1	0	0	0
T67	0	1024	0	0
T95	1	0	0	0
T96	1	0	0	0
T123	0	1024	0	0
T210	216	215	0	0
T217	1	0	0	0
T219	0	174	0	0
T220	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T9,T31,T39
0	1	Covered	T9,T31,T13
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T31,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T9,T31,T39
1	1	Covered	T9,T31,T13

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	3579	3554	0	0
selKnown1	3807	3777	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	3579	3554	0	0
T13	576	575	0	0
T23	1	0	0	0
T24	0	15	0	0
T25	0	21	0	0
T26	0	6	0	0
T29	1	0	0	0
T31	546	545	0	0
T39	1	0	0	0
T46	0	13	0	0
T47	546	545	0	0
T48	546	545	0	0
T67	0	575	0	0
T95	1	0	0	0
T96	1	0	0	0
T123	0	575	0	0
T220	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	3807	3777	0	0
T11	202	201	0	0
T12	1	0	0	0
T13	1025	1024	0	0
T24	0	11	0	0
T25	0	3	0	0
T26	0	13	0	0
T39	1	0	0	0
T46	0	21	0	0
T47	1	0	0	0
T67	0	1024	0	0
T95	1	0	0	0
T96	1	0	0	0
T123	0	1024	0	0
T210	216	215	0	0
T217	1	0	0	0
T219	0	174	0	0
T220	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T9,T31,T39
0	1	Covered	T9,T31,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T31,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T9,T31,T39
1	1	Covered	T9,T31,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	221	192	0	0
selKnown1	3773	3743	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	221	192	0	0
T11	1	0	0	0
T12	1	0	0	0
T13	2	1	0	0
T24	0	13	0	0
T25	0	10	0	0
T26	0	26	0	0
T31	2	1	0	0
T39	1	0	0	0
T46	0	6	0	0
T47	2	1	0	0
T48	0	1	0	0
T67	0	1	0	0
T95	1	0	0	0
T96	1	0	0	0
T123	0	1	0	0
T210	1	0	0	0
T217	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	3773	3743	0	0
T11	204	203	0	0
T12	1	0	0	0
T13	1025	1024	0	0
T23	1	0	0	0
T24	0	8	0	0
T25	0	1	0	0
T26	0	14	0	0
T39	1	0	0	0
T46	0	19	0	0
T47	1	0	0	0
T67	0	1025	0	0
T95	1	0	0	0
T96	1	0	0	0
T123	0	1024	0	0
T210	210	209	0	0
T217	1	0	0	0
T219	0	158	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T9,T31,T39
0	1	Covered	T9,T31,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T31,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T9,T31,T39
1	1	Covered	T9,T31,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	218	189	0	0
selKnown1	3771	3741	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	218	189	0	0
T11	1	0	0	0
T12	1	0	0	0
T13	2	1	0	0
T24	0	12	0	0
T25	0	10	0	0
T26	0	27	0	0
T31	2	1	0	0
T39	1	0	0	0
T46	0	6	0	0
T47	2	1	0	0
T48	0	1	0	0
T67	0	1	0	0
T95	1	0	0	0
T96	1	0	0	0
T123	0	1	0	0
T210	1	0	0	0
T217	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	3771	3741	0	0
T11	204	203	0	0
T12	1	0	0	0
T13	1025	1024	0	0
T23	1	0	0	0
T24	0	8	0	0
T25	0	1	0	0
T26	0	14	0	0
T39	1	0	0	0
T46	0	18	0	0
T47	1	0	0	0
T67	0	1025	0	0
T95	1	0	0	0
T96	1	0	0	0
T123	0	1024	0	0
T210	210	209	0	0
T217	1	0	0	0
T219	0	158	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T14 T15 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T39,T95
0	1	Covered	T9,T13,T23
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T14,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T39,T95
1	1	Covered	T9,T13,T23

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	552	530	0	0
selKnown1	27154	27119	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	530	0	0
T13	117	116	0	0
T23	1	0	0	0
T24	0	14	0	0
T25	11	10	0	0
T26	0	20	0	0
T29	1	0	0	0
T46	0	13	0	0
T67	117	116	0	0
T96	1	0	0	0
T123	117	116	0	0
T211	0	24	0	0
T212	0	24	0	0
T216	0	21	0	0
T220	1	0	0	0
T221	1	0	0	0
T222	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27154	27119	0	0
T11	383	382	0	0
T12	18	17	0	0
T13	1025	1024	0	0
T14	2	1	0	0
T15	20	19	0	0
T23	2	1	0	0
T51	20	19	0	0
T77	2	1	0	0
T210	401	400	0	0
T217	18	17	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T14 T15 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T39,T95
0	1	Covered	T9,T13,T23
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T14,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T39,T95
1	1	Covered	T9,T13,T23

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	542	520	0	0
selKnown1	27152	27117	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	542	520	0	0
T13	117	116	0	0
T23	1	0	0	0
T24	0	12	0	0
T25	10	9	0	0
T26	0	19	0	0
T29	1	0	0	0
T46	0	10	0	0
T67	117	116	0	0
T96	1	0	0	0
T123	117	116	0	0
T211	0	25	0	0
T212	0	24	0	0
T216	0	19	0	0
T220	1	0	0	0
T221	1	0	0	0
T222	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27152	27117	0	0
T11	383	382	0	0
T12	18	17	0	0
T13	1025	1024	0	0
T14	2	1	0	0
T15	20	19	0	0
T23	2	1	0	0
T51	20	19	0	0
T77	2	1	0	0
T210	401	400	0	0
T217	18	17	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T14 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T31,T33,T16
0	1	Covered	T9,T31,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T14,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T31,T33,T16
1	1	Covered	T9,T31,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	738	692	0	0
selKnown1	27116	27082	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	738	692	0	0
T11	1	0	0	0
T12	1	0	0	0
T13	0	1	0	0
T16	8	7	0	0
T17	2	1	0	0
T18	1	0	0	0
T31	135	134	0	0
T33	2	1	0	0
T39	1	0	0	0
T47	0	122	0	0
T66	31	30	0	0
T95	1	0	0	0
T223	0	1	0	0
T224	0	7	0	0
T225	0	33	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27116	27082	0	0
T11	386	385	0	0
T12	18	17	0	0
T13	1024	1023	0	0
T14	2	1	0	0
T15	20	19	0	0
T28	1	0	0	0
T51	20	19	0	0
T77	2	1	0	0
T78	0	1	0	0
T210	395	394	0	0
T217	18	17	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T9 T31 T14 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T31,T33,T16
0	1	Covered	T9,T31,T11
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T14,T11
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T31,T33,T16
1	1	Covered	T9,T31,T11

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	739	693	0	0
selKnown1	27114	27080	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	739	693	0	0
T11	1	0	0	0
T12	1	0	0	0
T13	0	1	0	0
T16	8	7	0	0
T17	2	1	0	0
T18	1	0	0	0
T31	135	134	0	0
T33	2	1	0	0
T39	1	0	0	0
T47	0	122	0	0
T66	31	30	0	0
T95	1	0	0	0
T223	0	1	0	0
T224	0	7	0	0
T225	0	33	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27114	27080	0	0
T11	386	385	0	0
T12	18	17	0	0
T13	1024	1023	0	0
T14	2	1	0	0
T15	20	19	0	0
T28	1	0	0	0
T51	20	19	0	0
T77	2	1	0	0
T78	0	1	0	0
T210	395	394	0	0
T217	18	17	0	0