Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T94,T156,T268	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T94,T155,T156	Yes	T94,T155,T156	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T229,T203,T86	Yes	T229,T203,T86	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T81,T229,T203	Yes	T81,T229,T203	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T221,T93,T155	Yes	T221,T93,T155	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T221,T92,T93	Yes	T221,T92,T93	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T230,T231,T232	Yes	T230,T231,T232	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T45,T40,T41	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T85,T86,T39	Yes	T85,T86,T39	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T45,T40,T41	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T45,T40,T41	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T85,T86,T39	Yes	T85,T86,T39	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T45,T40,T41	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T85,T86,T39	Yes	T85,T86,T39	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T85,T86,T39	Yes	T85,T86,T39	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T85,T39,T95	Yes	T85,T39,T95	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T85,T86,T39	Yes	T85,T86,T39	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T85,*T86,*T39	Yes	T85,T86,T39	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T85,T86,T39	Yes	T85,T86,T39	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T94,T156,T268	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T86,T56,T272	Yes	T86,T56,T272	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T86,T56,T272	Yes	T86,T56,T272	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T86,T56,T272	Yes	T86,T56,T272	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T86,T56,T272	Yes	T86,T56,T272	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T86,T56,T272	Yes	T86,T56,T272	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T86,*T56,*T272	Yes	T86,T56,T272	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T86,T56,T272	Yes	T86,T56,T272	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T45,T40,T41	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T86,T56,T272	Yes	T86,T56,T272	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T86,T56,T272	Yes	T86,T56,T272	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T45,T40,T41	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T86,*T56,*T272	Yes	T86,T56,T272	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T45,T40,T41	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T86,T56,T272	Yes	T86,T56,T272	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T197,T228	Yes	T1,T197,T228	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T197,T404,T95	Yes	T197,T404,T95	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T405,T283	Yes	T73,T405,T283	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T73,T405,T283	Yes	T73,T405,T283	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T73,T405,T283	Yes	T73,T405,T283	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T73,T405,T283	Yes	T73,T405,T283	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T73,T405,T283	Yes	T73,T405,T283	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T155,T156	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T405,T283,T406	Yes	T405,T283,T406	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T92,T94,T155	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T405,T283,T406	Yes	T73,T405,T283	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T155,T156	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T283,*T407,*T408	Yes	T405,T283,T406	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T73,T405,T283	Yes	T73,T405,T283	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T81,T436,T287	Yes	T81,T436,T287	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T11,T210,T219	Yes	T11,T210,T219	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T11,*T12,*T285	Yes	T11,T12,T285	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T11,T12,T285	Yes	T11,T12,T285	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T31,T285,T73	Yes	T31,T285,T73	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T31,T285,T73	Yes	T31,T285,T73	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T285,T73	Yes	T31,T285,T73	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T31,T285,T73	Yes	T31,T285,T73	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T31,T285,T73	Yes	T31,T285,T73	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T31,T285,T73	Yes	T31,T285,T73	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T31,T285,T73	Yes	T31,T285,T73	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T31,T285,T73	Yes	T31,T285,T73	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T31,T285,T120	Yes	T31,T285,T120	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T285,T120	Yes	T31,T285,T73	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T31,T285,T120	Yes	T31,T285,T120	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T31,*T285,*T120	Yes	T31,T285,T120	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T31,T285,T73	Yes	T31,T285,T73	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T2,T8,T10	Yes	T2,T8,T10	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T8,T10,T20	Yes	T8,T10,T20	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T8,T10	Yes	T2,T8,T10	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T2,T8,T10	Yes	T2,T8,T10	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T8,T10,T20	Yes	T8,T10,T20	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T2,T8,T10	Yes	T2,T8,T10	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T221,*T92,*T93	Yes	T221,T92,T93	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T2,T8,T10	Yes	T2,T8,T10	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T2,T8,T10	Yes	T2,T8,T10	INPUT
tl_usbdev_i.d_error	Yes	Yes	T92,T93,T155	Yes	T92,T93,T156	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T8,T10,T20	Yes	T2,T8,T10	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T8,T10	Yes	T8,T10,T20	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T2,T8,T10	Yes	T8,T10,T20	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T221,*T92,*T155	Yes	T221,T92,T93	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T8,*T10,*T20	Yes	T8,T10,T20	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T2,T8,T10	Yes	T2,T8,T10	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T9,T45,T27	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T9,T6,T45	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T94,T155	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T94,T155	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T94,T156,T268	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T92,T93,T156	Yes	T92,T93,T155	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T92,T155,T156	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T92,*T94,*T155	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T9,T31	Yes	T2,T9,T31	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T9,T45,T27	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T73,T317,T318	Yes	T73,T317,T318	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T317,T318	Yes	T73,T317,T318	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T73,T317,T318	Yes	T73,T317,T318	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T73,T317,T318	Yes	T73,T317,T318	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T73,T317,T318	Yes	T73,T317,T318	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T317,T318,T648	Yes	T317,T318,T648	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T73,T317,T318	Yes	T73,T317,T318	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T73,T317,T318	Yes	T73,T317,T318	INPUT
tl_hmac_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T317,T318,T648	Yes	T317,T318,T648	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T317,T318,T648	Yes	T317,T318,T648	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T73,T317,T318	Yes	T317,T318,T648	INPUT
tl_hmac_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T73,*T317,*T318	Yes	T317,T318,T648	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T73,T317,T318	Yes	T73,T317,T318	INPUT
tl_kmac_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T427,T73,T444	Yes	T427,T73,T444	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T40,T427,T233	Yes	T40,T427,T233	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T40,T427,T233	Yes	T40,T427,T233	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T427,T73,T444	Yes	T427,T73,T444	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T40,T427,T233	Yes	T40,T427,T233	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T39,*T92,*T93	Yes	T39,T92,T93	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T427,T444,T445	Yes	T427,T444,T445	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T40,T427,T233	Yes	T40,T427,T233	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T40,T427,T233	Yes	T40,T427,T233	INPUT
tl_kmac_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T40,T427,T233	Yes	T40,T427,T233	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T40,T427,T233	Yes	T40,T427,T233	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T40,T427,T233	Yes	T40,T427,T199	INPUT
tl_kmac_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T39,*T92,*T93	Yes	T39,T92,T93	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T40,*T427,*T233	Yes	T40,T427,T199	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T40,T427,T233	Yes	T40,T427,T233	INPUT
tl_aes_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T294,T295,T73	Yes	T294,T295,T73	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T294,T295,T73	Yes	T294,T295,T73	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T294,T295,T73	Yes	T294,T295,T73	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T294,T295,T73	Yes	T294,T295,T73	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T294,T295,T73	Yes	T294,T295,T73	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T96,*T92,*T93	Yes	T96,T92,T93	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T294,T295,T73	Yes	T294,T295,T73	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T294,T295,T73	Yes	T294,T295,T73	INPUT
tl_aes_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T294,T295,T383	Yes	T294,T295,T383	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T294,T295,T383	Yes	T294,T295,T73	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T294,T295,T383	Yes	T294,T295,T73	INPUT
tl_aes_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T96,*T92,*T155	Yes	T96,T92,T93	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T294,*T295,*T383	Yes	T294,T295,T383	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T294,T295,T73	Yes	T294,T295,T73	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T92,*T94,*T155	Yes	T92,T93,T94	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T152,*T153,*T154	Yes	T152,T153,T154	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T73,T384,T152	Yes	T73,T384,T152	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T96,*T92,*T93	Yes	T96,T92,T93	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T384,T152,T338	Yes	T384,T152,T338	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T96,*T92,*T155	Yes	T96,T92,T93	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T384,*T152,*T338	Yes	T384,T152,T338	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T73,T384,T152	Yes	T73,T384,T152	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T73,T384,T152	Yes	T73,T384,T152	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T92,T93,T155	Yes	T92,T155,T156	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T384,T152,T154	Yes	T384,T152,T154	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T384,*T152,*T154	Yes	T384,T152,T154	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T73,T152,T154	Yes	T73,T152,T154	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T152,T154	Yes	T73,T152,T154	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T73,T152,T154	Yes	T73,T152,T154	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T73,T152,T154	Yes	T73,T152,T154	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T73,T152,T154	Yes	T73,T152,T154	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T73,T152,T154	Yes	T73,T152,T154	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T73,T152,T154	Yes	T73,T152,T154	INPUT
tl_edn1_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T152,T154,T149	Yes	T152,T154,T149	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T154,T149,T263	Yes	T73,T152,T154	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T154,T149,T263	Yes	T73,T152,T154	INPUT
tl_edn1_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T152,*T154,*T149	Yes	T152,T154,T149	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T73,T152,T154	Yes	T73,T152,T154	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T9,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_otbn_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T207,T73,T154	Yes	T207,T73,T154	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T207,T73,T154	Yes	T207,T73,T154	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T207,T73,T154	Yes	T207,T73,T154	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T207,T73,T154	Yes	T207,T73,T154	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T207,T73,T154	Yes	T207,T73,T154	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T39,*T95,*T220	Yes	T39,T95,T220	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T207,T73,T154	Yes	T207,T73,T154	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T207,T73,T154	Yes	T207,T73,T154	INPUT
tl_otbn_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T207,T154,T149	Yes	T207,T154,T149	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T207,T154,T149	Yes	T207,T154,T149	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T207,T73,T154	Yes	T207,T154,T149	INPUT
tl_otbn_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T39,*T95,*T220	Yes	T39,T95,T220	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T207,*T73,*T154	Yes	T207,T154,T149	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T207,T73,T154	Yes	T207,T73,T154	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T40,T233,T73	Yes	T40,T233,T73	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T40,T233,T73	Yes	T40,T233,T73	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T40,T233,T73	Yes	T40,T233,T73	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T40,T73,T199	Yes	T40,T73,T199	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T40,T233,T73	Yes	T40,T233,T73	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T40,T233,T73	Yes	T40,T233,T73	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T40,T233,T73	Yes	T40,T233,T73	INPUT
tl_keymgr_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T40,T199,T234	Yes	T40,T199,T234	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T40,T199,T234	Yes	T40,T73,T199	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T40,T199,T234	Yes	T40,T73,T199	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T40,*T199,*T234	Yes	T40,T233,T199	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T40,T233,T73	Yes	T40,T233,T73	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T56,*T272,*T92	Yes	T56,T272,T92	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T9,T31,T5	Yes	T9,T31,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T9,T31,T5	Yes	T9,T31,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T56,T272,T92	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T439,*T92,*T93	Yes	T439,T92,T93	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T203,T309,T310	Yes	T203,T309,T310	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T142,T200,T203	Yes	T73,T142,T200	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T142,T200,T203	Yes	T73,T142,T200	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T155	Yes	T439,T92,T93	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T142,*T200,*T203	Yes	T142,T200,T203	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T9,T45,T27	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range