Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T81,T436,T287	Yes	T81,T436,T287	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T113,T124,T239	Yes	T113,T124,T239	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T113,T124,T239	Yes	T113,T124,T239	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T113,T124,T73	Yes	T113,T124,T73	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T113,T124,T73	Yes	T113,T124,T73	INPUT
tl_uart0_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T113,T124,T315	Yes	T113,T124,T315	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T113,T124,T183	Yes	T113,T124,T73	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T113,T124,T183	Yes	T113,T124,T73	INPUT
tl_uart0_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T56,*T272,*T659	Yes	T56,T272,T659	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T92,T93,T155	Yes	T92,T93,T155	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T113,*T124,*T315	Yes	T113,T124,T315	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T113,T124,T73	Yes	T113,T124,T73	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T114,T315,T13	Yes	T114,T315,T13	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T114,T315,T13	Yes	T114,T315,T13	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T114,T73,T183	Yes	T114,T73,T183	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T114,T73,T183	Yes	T114,T73,T183	INPUT
tl_uart1_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T114,T315,T13	Yes	T114,T315,T13	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T114,T183,T315	Yes	T114,T73,T183	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T114,T183,T315	Yes	T114,T73,T183	INPUT
tl_uart1_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T221,*T92,*T155	Yes	T221,T92,T93	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T114,*T315,*T13	Yes	T114,T315,T13	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T114,T73,T183	Yes	T114,T73,T183	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T35,T63,T64	Yes	T35,T63,T64	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T35,T63,T64	Yes	T35,T63,T64	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T35,T63,T64	Yes	T35,T63,T64	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T35,T63,T64	Yes	T35,T63,T64	INPUT
tl_uart2_i.d_error	Yes	Yes	T92,T93,T155	Yes	T92,T93,T94	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T35,T63,T64	Yes	T35,T63,T64	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T35,T63,T64	Yes	T35,T63,T64	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T35,T63,T64	Yes	T35,T63,T64	INPUT
tl_uart2_i.d_sink	Yes	Yes	T92,T93,T155	Yes	T92,T93,T155	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T221,*T92,*T93	Yes	T221,T92,T93	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T35,*T63,*T64	Yes	T35,T63,T64	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T35,T63,T64	Yes	T35,T63,T64	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T30,T315,T13	Yes	T30,T315,T13	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T30,T315,T13	Yes	T30,T315,T13	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T30,T73,T183	Yes	T30,T73,T183	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T30,T73,T183	Yes	T30,T73,T183	INPUT
tl_uart3_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T156	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T30,T315,T13	Yes	T30,T315,T13	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T183,T315	Yes	T30,T73,T183	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T30,T183,T315	Yes	T30,T73,T183	INPUT
tl_uart3_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T221,*T92,*T155	Yes	T221,T92,T93	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T30,*T315,*T13	Yes	T30,T315,T13	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T30,T73,T183	Yes	T30,T73,T183	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T58,T285,T306	Yes	T58,T285,T306	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T58,T285,T306	Yes	T58,T285,T306	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T58,T285,T73	Yes	T58,T285,T73	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T58,T285,T73	Yes	T58,T285,T73	INPUT
tl_i2c0_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T58,T306,T13	Yes	T58,T306,T13	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T58,T285,T183	Yes	T58,T285,T73	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T58,T285,T183	Yes	T58,T285,T73	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T58,*T285,*T306	Yes	T58,T285,T306	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T58,T285,T73	Yes	T58,T285,T73	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T60,T285,T306	Yes	T60,T285,T306	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T60,T285,T306	Yes	T60,T285,T306	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T60,T285,T73	Yes	T60,T285,T73	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T60,T285,T73	Yes	T60,T285,T73	INPUT
tl_i2c1_i.d_error	Yes	Yes	T92,T93,T155	Yes	T92,T93,T155	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T60,T306,T13	Yes	T60,T306,T13	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T285,T183	Yes	T60,T285,T73	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T60,T285,T183	Yes	T60,T285,T73	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T155	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T60,*T285,*T306	Yes	T60,T285,T306	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T60,T285,T73	Yes	T60,T285,T73	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T34,T62,T285	Yes	T34,T62,T285	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T34,T62,T285	Yes	T34,T62,T285	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T34,T62,T285	Yes	T34,T62,T285	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T34,T62,T285	Yes	T34,T62,T285	INPUT
tl_i2c2_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T34,T62,T306	Yes	T34,T62,T306	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T62,T285	Yes	T34,T62,T285	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T34,T62,T285	Yes	T34,T62,T285	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T92,T155,T156	Yes	T92,T93,T94	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T92,T155,T156	Yes	T92,T94,T155	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T34,*T62,*T285	Yes	T34,T62,T285	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T34,T62,T285	Yes	T34,T62,T285	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T5,T120,T39	Yes	T5,T120,T39	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T5,T120,T39	Yes	T5,T120,T39	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T5,T73,T120	Yes	T5,T73,T120	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T5,T73,T120	Yes	T5,T73,T120	INPUT
tl_pattgen_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T5,T120,T39	Yes	T5,T120,T39	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T120,T39	Yes	T5,T73,T120	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T5,T120,T39	Yes	T5,T73,T120	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T39,T92,*T93	Yes	T39,T92,T93	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T5,*T120,*T39	Yes	T5,T120,T39	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T5,T73,T120	Yes	T5,T73,T120	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T37,T122,T128	Yes	T37,T122,T128	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T37,T122,T128	Yes	T37,T122,T128	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T37,T73,T122	Yes	T37,T73,T122	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T37,T73,T122	Yes	T37,T73,T122	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T37,T122,T128	Yes	T37,T122,T128	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T122,T128	Yes	T37,T73,T122	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T37,T122,T128	Yes	T37,T73,T122	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T37,*T122,*T128	Yes	T37,T122,T128	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T37,T73,T122	Yes	T37,T73,T122	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T14,T32,T306	Yes	T14,T32,T306	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T14,T32,T306	Yes	T7,T14,T32	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T14,T32,T306	Yes	T7,T14,T32	INPUT
tl_gpio_i.d_sink	Yes	Yes	T92,T93,T155	Yes	T92,T155,T156	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T94,T155	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T9,*T7,*T45	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T11	Yes	T14,T15,T11	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T14,T15,T11	Yes	T14,T15,T11	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T14,T15,T11	Yes	T14,T15,T11	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T14,T15,T11	Yes	T14,T15,T11	INPUT
tl_spi_device_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T15,T11,T12	Yes	T15,T11,T12	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T11	Yes	T14,T15,T11	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T14,T15,T11	Yes	T15,T11,T12	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T14,*T15,*T11	Yes	T14,T15,T11	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T14,T15,T11	Yes	T14,T15,T11	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T119,T257,T639	Yes	T119,T257,T639	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T119,T257,T639	Yes	T119,T257,T639	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T119,T257,T73	Yes	T119,T257,T73	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T119,T257,T73	Yes	T119,T257,T73	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T119,T257,T639	Yes	T119,T257,T639	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T119,T257,T639	Yes	T119,T257,T73	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T119,T257,T639	Yes	T119,T257,T73	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T119,*T257,*T639	Yes	T119,T257,T639	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T119,T257,T73	Yes	T119,T257,T73	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T9,T7,T14	Yes	T9,T7,T14	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T9,T7,T14	Yes	T9,T7,T14	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T9,T7,T14	Yes	T9,T7,T14	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T9,T7,T14	Yes	T9,T7,T14	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T9,T7,T14	Yes	T9,T7,T14	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T7,T14	Yes	T9,T7,T14	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T9,T7,T14	Yes	T9,T7,T14	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T92,*T94,*T155	Yes	T92,T93,T94	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T9,*T7,*T14	Yes	T9,T7,T14	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T9,T7,T14	Yes	T9,T7,T14	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T27,T40	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T45,T27,T40	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T92,*T94,*T155	Yes	T92,T93,T94	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T113,T30,T114	Yes	T113,T30,T114	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T113,T30,T114	Yes	T113,T30,T114	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T113,T30,T114	Yes	T113,T30,T114	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T113,T30	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T45,T113,T30	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T96,*T92,*T155	Yes	T176,T96,T177	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T113,*T30,*T114	Yes	T113,T30,T114	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T39,*T92,*T93	Yes	T39,T92,T93	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T39,*T176,*T177	Yes	T39,T176,T177	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T92,T93,T155	Yes	T92,T93,T94	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T40,*T38,*T178	Yes	T40,T178,T179	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T39,T92,T93	Yes	T39,T92,T93	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T39,T92,T93	Yes	T39,T92,T93	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T39,T92,T93	Yes	T39,T92,T93	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T45,T41,T79	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T39,T92,T93	Yes	T39,T92,T93	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T92,T93	Yes	T39,T92,T93	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T45,T41,T79	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T155	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T39,T92,T155	Yes	T39,T92,T93	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T45,T41,T79	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T39,T92,T93	Yes	T39,T92,T93	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T6,T35,T40	Yes	T6,T35,T40	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T6,T35,T40	Yes	T6,T35,T40	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T6,T35,T40	Yes	T6,T35,T40	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T6,T35,T40	Yes	T6,T35,T40	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T40,T179,T192	Yes	T6,T40,T179	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T192,T188,T150	Yes	T192,T73,T188	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T40,T179,T192	Yes	T6,T35,T40	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T86,*T39,*T365	Yes	T86,T39,T365	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T40,*T192,*T199	Yes	T6,T35,T40	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T6,T35,T40	Yes	T6,T35,T40	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T172,T158,T163	Yes	T172,T158,T163	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T172,T158,T163	Yes	T73,T172,T158	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T45,T40,T41	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T94,T155	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T92,*T94,*T155	Yes	T92,T93,T155	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T45,*T40,*T41	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T45,T79,T81	Yes	T45,T79,T81	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T45,T79,T81	Yes	T45,T79,T81	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T45,T79,T81	Yes	T45,T79,T81	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T45,T79,T81	Yes	T45,T79,T81	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T92,T94,T450	Yes	T92,T93,T94	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T45,T79,T81	Yes	T45,T79,T81	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T79,T81	Yes	T45,T79,T81	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T45,T79,T81	Yes	T45,T79,T81	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T96,*T92,*T155	Yes	T96,T92,T93	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T94,T155	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T45,*T79,*T81	Yes	T45,T79,T81	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T45,T79,T81	Yes	T45,T79,T81	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T142,T200,T202	Yes	T142,T200,T202	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T142,T200,T202	Yes	T142,T200,T202	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T142,T200,T202	Yes	T142,T200,T202	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T142,T200,T202	Yes	T73,T142,T200	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T142,T200,T202	Yes	T73,T142,T200	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T155	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T142,*T200,*T202	Yes	T142,T200,T202	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T73,T142,T200	Yes	T73,T142,T200	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T45,T255,T27	Yes	T45,T255,T27	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T45,T40,T36	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T45,T255,T79	Yes	T45,T255,T79	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T255,T40	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T45,T79,T81	Yes	T45,T79,T81	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T95,*T56,*T220	Yes	T95,T56,T220	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T45,T255,T79	Yes	T45,T255,T79	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T45,T255,T79	Yes	T45,T255,T79	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T45,T255,T79	Yes	T45,T255,T79	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T45,T255,T79	Yes	T45,T255,T79	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T92,T93,T155	Yes	T92,T93,T155	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T45,T255,T79	Yes	T45,T255,T79	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T255,T79	Yes	T45,T255,T79	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T45,T255,T79	Yes	T45,T255,T79	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T92,T93,T155	Yes	T92,T93,T94	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T96,*T92,*T155	Yes	T56,T659,T660	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T155	Yes	T92,T93,T94	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T45,*T255,*T79	Yes	T45,T255,T79	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T45,T255,T79	Yes	T45,T255,T79	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T33,T16,T19	Yes	T33,T16,T19	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T33,T16,T19	Yes	T33,T16,T19	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T33,T16,T19	Yes	T33,T16,T19	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T33,T16,T19	Yes	T33,T16,T19	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T94,T155	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T33,T16,T19	Yes	T33,T16,T19	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T19,T66	Yes	T16,T19,T73	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T33,T16,T19	Yes	T33,T16,T19	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T92,T94,T155	Yes	T92,T93,T94	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T221,*T92,*T155	Yes	T221,T92,T93	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T155	Yes	T92,T93,T94	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T16,*T19,*T66	Yes	T33,T16,T19	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T33,T16,T19	Yes	T33,T16,T19	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T133,T69,T306	Yes	T133,T69,T306	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T133,T69,T306	Yes	T133,T69,T306	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T73,T133,T69	Yes	T73,T133,T69	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T73,T133,T69	Yes	T73,T133,T69	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T92,T93,T156	Yes	T92,T93,T94	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T133,T69,T306	Yes	T133,T69,T306	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T133,T69,T306	Yes	T73,T133,T69	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T133,T69,T87	Yes	T73,T133,T69	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T92,T93,T155	Yes	T92,T93,T94	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T96,*T92,*T93	Yes	T96,T92,T93	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T155	Yes	T92,T93,T155	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T133,*T69,*T306	Yes	T133,T69,T306	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T73,T133,T69	Yes	T73,T133,T69	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T86,*T39,*T95	Yes	T86,T39,T95	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T39,T95,T96	Yes	T39,T95,T96	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T92,T94,T155	Yes	T92,T94,T155	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T9,T45,T27	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T92,*T155,*T156	Yes	T92,T93,T94	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range