Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3952040	1			T96	80		T97	69		T98	820
values[2]	796181	1			T96	41		T97	33		T98	199
values[3]	104462	1			T97	1		T155	1		T230	1
values[4]	55154	1			T437	1		T536	180		T542	1
values[5]	37696	1			T536	144		T544	11		T631	48
values[6]	28250	1			T536	126		T544	8		T631	62
values[7]	23158	1			T536	96		T544	2		T631	92
values[8]	19963	1			T536	85		T631	59		T533	2
values[9]	17841	1			T536	48		T631	50		T533	1
values[10]	15908	1			T536	32		T631	37		T533	1
values[11]	14891	1			T536	30		T631	44		T533	1
values[12]	14051	1			T536	23		T631	45		T533	1
values[13]	13545	1			T536	15		T631	56		T533	12
values[14]	12805	1			T536	10		T631	50		T533	6
values[15]	12431	1			T536	13		T631	57		T533	3
values[16]	11711	1			T536	7		T631	77		T533	2
values[17]	11493	1			T536	1		T631	69		T533	2
values[18]	10904	1			T536	2		T631	75		T533	1
values[19]	10586	1			T536	4		T631	50		T533	3
values[20]	10125	1			T536	2		T631	49		T533	4
values[21]	10026	1			T536	1		T631	46		T533	2
values[22]	9615	1			T536	1		T631	49		T533	1
values[23]	9525	1			T536	3		T631	53		T533	1
values[24]	9067	1			T536	2		T631	54		T533	1
values[25]	8798	1			T536	2		T631	37		T533	2
values[26]	8471	1			T536	1		T631	28		T533	3
values[27]	7931	1			T536	2		T631	33		T533	4
values[28]	7192	1			T536	4		T631	29		T533	1
values[29]	6938	1			T536	3		T631	24		T533	2
values[30]	6524	1			T536	1		T631	24		T533	1
values[31]	6065	1			T536	1		T631	18		T533	4
values[32]	5759	1			T536	2		T631	28		T533	9
values[33]	5350	1			T536	2		T631	17		T533	6
values[34]	5103	1			T536	2		T631	18		T533	2
values[35]	4682	1			T536	1		T631	18		T533	2
values[36]	4491	1			T536	1		T631	33		T533	9
values[37]	4224	1			T536	1		T631	19		T533	5
values[38]	4048	1			T536	1		T631	7		T533	1
values[39]	3866	1			T536	2		T631	1		T533	3
values[40]	3712	1			T536	1		T631	1		T533	1
values[41]	3494	1			T536	1		T631	1		T533	3
values[42]	3434	1			T536	1		T631	2		T533	3
values[43]	3310	1			T536	1		T631	4		T533	1
values[44]	3228	1			T536	2		T631	4		T533	1
values[45]	3217	1			T536	2		T631	2		T533	1
values[46]	3206	1			T536	3		T631	1		T533	4
values[47]	3098	1			T536	2		T631	1		T533	2
values[48]	3002	1			T536	2		T631	1		T533	2
values[49]	3020	1			T536	1		T631	2		T533	2
values[50]	2947	1			T536	2		T631	2		T533	2
values[51]	2887	1			T536	1		T631	2		T533	1
values[52]	2872	1			T536	1		T631	1		T533	1
values[53]	2762	1			T536	3		T631	3		T533	1
values[54]	2700	1			T536	1		T533	2		T575	3
values[55]	2627	1			T536	1		T533	4		T575	3
values[56]	2542	1			T536	2		T533	1		T575	3
values[57]	2589	1			T536	2		T533	3		T575	3
values[58]	2492	1			T536	1		T533	2		T575	2
values[59]	2482	1			T536	2		T533	1		T575	5
values[60]	2490	1			T536	1		T533	1		T575	6
values[61]	2736	1			T536	1		T533	4		T575	4
values[62]	4187	1			T536	6		T533	6		T575	6
values[63]	11222	1			T536	6		T533	52		T575	13
values[64]	227709	1			T536	87		T533	75		T575	20

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	5020733	1			T96	164		T97	94		T98	1039
values[2]	849121	1			T96	21		T97	16		T98	290
values[3]	84761	1			T97	1		T98	10		T102	5
values[4]	14832	1			T547	4		T437	5		T536	1
values[5]	5620	1			T542	4		T434	1		T544	6
values[6]	3242	1			T542	1		T544	1		T829	7
values[7]	2389	1			T829	7		T551	21		T632	1
values[8]	2217	1			T829	9		T551	15		T493	2
values[9]	1993	1			T829	10		T551	13		T493	3
values[10]	1796	1			T829	10		T551	21		T493	2
values[11]	1595	1			T829	8		T551	25		T493	1
values[12]	1431	1			T829	7		T551	11		T493	2
values[13]	1402	1			T829	12		T551	18		T493	2
values[14]	1236	1			T829	1		T551	17		T493	1
values[15]	1131	1			T551	11		T493	1		T629	3
values[16]	1111	1			T551	21		T493	1		T629	1
values[17]	998	1			T551	21		T493	2		T629	1
values[18]	1016	1			T551	21		T493	3		T629	2
values[19]	960	1			T551	13		T493	1		T629	2
values[20]	953	1			T551	7		T493	4		T629	2
values[21]	927	1			T551	5		T493	2		T629	2
values[22]	857	1			T551	4		T493	5		T629	2
values[23]	767	1			T551	4		T493	1		T629	2
values[24]	691	1			T551	5		T493	1		T629	2
values[25]	745	1			T551	16		T493	3		T629	2
values[26]	699	1			T551	11		T493	7		T629	2
values[27]	577	1			T551	10		T493	1		T629	2
values[28]	584	1			T551	12		T493	1		T629	2
values[29]	577	1			T551	14		T493	3		T629	2
values[30]	587	1			T551	9		T493	2		T629	2
values[31]	613	1			T551	6		T493	1		T629	1
values[32]	606	1			T551	14		T493	1		T629	2
values[33]	583	1			T551	17		T493	1		T629	2
values[34]	558	1			T551	12		T493	3		T629	2
values[35]	539	1			T551	5		T493	2		T629	2
values[36]	518	1			T551	4		T493	1		T629	2
values[37]	490	1			T551	5		T493	2		T629	2
values[38]	497	1			T551	10		T493	3		T629	2
values[39]	479	1			T551	7		T493	3		T629	2
values[40]	430	1			T551	5		T493	2		T629	3
values[41]	443	1			T551	4		T493	5		T629	2
values[42]	428	1			T551	8		T493	2		T629	2
values[43]	432	1			T551	4		T493	2		T629	2
values[44]	449	1			T551	2		T493	1		T629	2
values[45]	423	1			T551	2		T493	2		T629	2
values[46]	446	1			T551	1		T493	4		T629	2
values[47]	447	1			T551	2		T493	7		T629	2
values[48]	403	1			T551	2		T493	2		T629	2
values[49]	413	1			T551	1		T493	1		T629	2
values[50]	391	1			T551	2		T493	1		T629	2
values[51]	357	1			T551	3		T493	1		T629	2
values[52]	380	1			T551	4		T493	1		T629	2
values[53]	365	1			T551	2		T493	4		T629	2
values[54]	399	1			T551	14		T493	1		T629	2
values[55]	407	1			T551	11		T493	2		T629	2
values[56]	383	1			T551	12		T493	1		T629	2
values[57]	398	1			T551	14		T493	3		T629	2
values[58]	403	1			T551	16		T493	2		T629	2
values[59]	391	1			T551	3		T493	1		T629	2
values[60]	371	1			T493	2		T629	2		T796	2
values[61]	453	1			T493	1		T629	2		T796	9
values[62]	674	1			T493	1		T629	2		T796	8
values[63]	2508	1			T493	5		T629	3		T796	26
values[64]	26110	1			T493	67		T629	132		T796	53

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	588766	1			T96	1		T97	2		T98	8
values[2]	2859360	1			T96	56		T97	75		T98	783
values[3]	1235225	1			T96	50		T97	62		T98	224
values[4]	145730	1			T97	1		T102	6		T155	1
values[5]	74466	1			T536	154		T544	17		T631	73
values[6]	49243	1			T536	127		T544	17		T631	51
values[7]	36362	1			T536	66		T544	3		T631	46
values[8]	29017	1			T536	64		T544	2		T631	54
values[9]	24536	1			T536	59		T631	54		T533	7
values[10]	21443	1			T536	75		T631	48		T533	5
values[11]	19263	1			T536	44		T631	57		T533	2
values[12]	17394	1			T536	36		T631	71		T533	4
values[13]	16560	1			T536	15		T631	57		T533	2
values[14]	15689	1			T536	20		T631	36		T533	1
values[15]	15019	1			T536	20		T631	51		T533	1
values[16]	14193	1			T536	23		T631	54		T533	2
values[17]	13721	1			T536	27		T631	49		T533	2
values[18]	13169	1			T536	7		T631	57		T533	3
values[19]	12578	1			T536	3		T631	53		T533	10
values[20]	11822	1			T536	1		T631	35		T533	5
values[21]	11749	1			T536	6		T631	63		T533	3
values[22]	11237	1			T536	1		T631	68		T533	3
values[23]	10770	1			T536	1		T631	56		T533	2
values[24]	10468	1			T536	5		T631	59		T533	1
values[25]	10087	1			T536	4		T631	35		T533	1
values[26]	9341	1			T536	2		T631	46		T533	2
values[27]	9031	1			T536	1		T631	59		T533	6
values[28]	8410	1			T536	2		T631	66		T533	5
values[29]	7992	1			T536	2		T631	65		T533	2
values[30]	7478	1			T536	3		T631	40		T533	1
values[31]	6969	1			T536	2		T631	22		T533	2
values[32]	6455	1			T536	4		T631	12		T533	5
values[33]	5880	1			T536	1		T631	6		T533	2
values[34]	5522	1			T536	5		T631	10		T533	2
values[35]	5166	1			T536	6		T631	13		T533	4
values[36]	4872	1			T536	4		T631	8		T533	2
values[37]	4651	1			T536	3		T631	12		T533	2
values[38]	4468	1			T536	3		T631	5		T533	2
values[39]	4239	1			T536	3		T631	12		T533	2
values[40]	4083	1			T536	3		T631	6		T533	1
values[41]	3869	1			T536	1		T631	9		T533	1
values[42]	3816	1			T536	2		T631	6		T533	2
values[43]	3722	1			T536	7		T631	7		T533	1
values[44]	3723	1			T536	10		T631	4		T533	1
values[45]	3561	1			T536	10		T631	5		T533	3
values[46]	3587	1			T536	7		T631	8		T533	2
values[47]	3500	1			T536	5		T631	4		T533	5
values[48]	3426	1			T536	4		T631	11		T533	4
values[49]	3346	1			T536	1		T631	13		T533	1
values[50]	3360	1			T536	5		T631	12		T533	2
values[51]	3093	1			T536	4		T631	10		T533	1
values[52]	3291	1			T536	3		T631	6		T533	1
values[53]	3174	1			T536	2		T631	7		T533	3
values[54]	3021	1			T536	4		T631	6		T533	2
values[55]	2983	1			T536	4		T631	14		T533	2
values[56]	2873	1			T536	2		T631	7		T533	2
values[57]	2819	1			T536	4		T631	9		T533	4
values[58]	2813	1			T536	2		T631	4		T533	7
values[59]	2773	1			T536	6		T631	4		T533	3
values[60]	2774	1			T536	2		T631	9		T533	1
values[61]	2923	1			T536	3		T631	1		T533	2
values[62]	3914	1			T536	3		T533	9		T534	5
values[63]	9369	1			T536	1		T533	22		T534	14
values[64]	221207	1			T536	6		T533	70		T534	115