Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2160231	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35680326

1

T1

350

T2

4597

T3

4435

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26103267	1			T1	175		T2	1368		T3	1487
values[0x0]	10259521	1			T1	175		T2	3229		T3	2948
values[0x1]	1477769	1			T1	3		T2	96		T3	247

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	785227	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37055330

1

T1

353

T2

4693

T3

4682

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17527664	1			T1	177		T2	2347		T3	2341
valid_sources[0x01]	17528032	1			T1	176		T2	2346		T3	2341
valid_sources[0x02]	44656	1			T404	17		T163	53		T406	10
valid_sources[0x03]	44888	1			T224	1		T225	1		T404	27
valid_sources[0x04]	45109	1			T37	8		T224	1		T404	20
valid_sources[0x05]	44254	1			T404	16		T875	12		T163	95
valid_sources[0x06]	44970	1			T100	2		T224	6		T404	23
valid_sources[0x07]	44607	1			T404	13		T875	27		T163	101
valid_sources[0x08]	44887	1			T225	1		T404	14		T163	75
valid_sources[0x09]	44633	1			T100	1		T225	2		T404	16
valid_sources[0x0a]	44532	1			T100	3		T224	1		T225	1
valid_sources[0x0b]	45037	1			T225	1		T404	22		T163	70
valid_sources[0x0c]	45191	1			T404	18		T875	19		T163	85
valid_sources[0x0d]	44958	1			T100	1		T225	1		T404	10
valid_sources[0x0e]	45028	1			T225	1		T404	17		T163	51
valid_sources[0x0f]	44428	1			T225	2		T404	6		T163	73
valid_sources[0x10]	45104	1			T224	1		T225	1		T404	12
valid_sources[0x11]	45347	1			T404	9		T875	25		T163	128
valid_sources[0x12]	44335	1			T224	1		T225	2		T404	17
valid_sources[0x13]	44365	1			T404	26		T163	68		T406	22
valid_sources[0x14]	45068	1			T224	1		T225	1		T404	18
valid_sources[0x15]	44221	1			T37	3		T100	3		T224	2
valid_sources[0x16]	44783	1			T225	1		T404	26		T163	77
valid_sources[0x17]	44584	1			T100	1		T224	1		T225	1
valid_sources[0x18]	44784	1			T37	11		T224	1		T225	1
valid_sources[0x19]	46393	1			T224	3		T404	21		T163	62
valid_sources[0x1a]	45165	1			T37	4		T100	1		T404	18
valid_sources[0x1b]	44867	1			T100	1		T404	24		T875	26
valid_sources[0x1c]	44312	1			T404	20		T875	12		T163	66
valid_sources[0x1d]	45072	1			T100	1		T225	1		T404	12
valid_sources[0x1e]	45208	1			T224	1		T404	12		T163	86
valid_sources[0x1f]	44619	1			T100	2		T404	16		T163	86
valid_sources[0x20]	45311	1			T101	39		T224	1		T404	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25197152

1

T1

175

T2

1368

T3

1487

values[0x0]

all_enables

biggest_size

10208875

1

T1

175

T2

3229

T3

2948

values[0x1]

all_enables

biggest_size

274299

1

T37

19

T100

17

T101

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2934456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

463396

1

T96

17

T97

8

T98

132

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1152104	1			T96	33		T97	44		T98	355
values[0x0]	1095318	1			T96	50		T97	26		T98	334
values[0x1]	1150430	1			T96	38		T97	33		T98	330

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2271868	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1125984

1

T96

36

T97

29

T98

342

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53135	1			T98	12		T102	3		T155	3
valid_sources[0x01]	52909	1			T96	3		T98	14		T102	2
valid_sources[0x02]	53281	1			T97	9		T98	16		T102	4
valid_sources[0x03]	53703	1			T96	6		T98	15		T102	2
valid_sources[0x04]	53071	1			T96	3		T98	18		T102	2
valid_sources[0x05]	52879	1			T96	1		T98	16		T102	5
valid_sources[0x06]	52458	1			T96	1		T98	11		T102	7
valid_sources[0x07]	52893	1			T96	3		T98	25		T102	2
valid_sources[0x08]	53706	1			T96	3		T97	2		T98	22
valid_sources[0x09]	53634	1			T96	1		T98	13		T102	2
valid_sources[0x0a]	52869	1			T96	2		T98	12		T102	2
valid_sources[0x0b]	52949	1			T96	1		T98	13		T102	2
valid_sources[0x0c]	53497	1			T96	3		T98	12		T102	4
valid_sources[0x0d]	52700	1			T96	1		T98	24		T155	7
valid_sources[0x0e]	52830	1			T96	1		T98	12		T102	1
valid_sources[0x0f]	52207	1			T96	1		T97	5		T98	18
valid_sources[0x10]	53334	1			T97	5		T98	12		T102	1
valid_sources[0x11]	53764	1			T98	13		T102	2		T155	8
valid_sources[0x12]	53537	1			T96	1		T97	8		T98	14
valid_sources[0x13]	52908	1			T96	2		T97	2		T98	15
valid_sources[0x14]	54141	1			T96	4		T98	16		T155	16
valid_sources[0x15]	52525	1			T96	1		T98	13		T155	13
valid_sources[0x16]	52564	1			T96	2		T97	3		T98	12
valid_sources[0x17]	52358	1			T96	2		T98	14		T102	2
valid_sources[0x18]	51832	1			T96	1		T98	17		T102	3
valid_sources[0x19]	53949	1			T96	2		T97	2		T98	20
valid_sources[0x1a]	53178	1			T96	1		T98	13		T102	4
valid_sources[0x1b]	52400	1			T96	2		T98	15		T102	3
valid_sources[0x1c]	52910	1			T96	4		T98	15		T155	5
valid_sources[0x1d]	53140	1			T96	2		T97	1		T98	15
valid_sources[0x1e]	53783	1			T96	4		T97	12		T98	12
valid_sources[0x1f]	54070	1			T96	3		T97	1		T98	15
valid_sources[0x20]	52431	1			T97	16		T98	19		T102	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49021

1

T97

1

T98

14

T102

1

values[0x0]

all_enables

biggest_size

365809

1

T96

15

T97

6

T98

109

values[0x1]

all_enables

biggest_size

48566

1

T96

2

T97

1

T98

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3130525	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

509794

1

T96

32

T97

9

T98

203

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1248762	1			T96	60		T97	39		T98	490
values[0x0]	1145249	1			T96	73		T97	29		T98	430
values[0x1]	1246308	1			T96	52		T97	43		T98	419

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2401431	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1238888

1

T96

63

T97

36

T98

496

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57153	1			T96	2		T97	1		T98	22
valid_sources[0x01]	56793	1			T96	5		T97	2		T98	24
valid_sources[0x02]	57156	1			T96	3		T97	1		T98	37
valid_sources[0x03]	56517	1			T96	3		T97	1		T98	18
valid_sources[0x04]	56956	1			T96	2		T97	2		T155	6
valid_sources[0x05]	57211	1			T96	5		T97	4		T98	4
valid_sources[0x06]	55887	1			T96	2		T97	3		T98	8
valid_sources[0x07]	56532	1			T96	3		T97	8		T98	18
valid_sources[0x08]	56714	1			T96	3		T97	2		T98	42
valid_sources[0x09]	57448	1			T96	2		T97	2		T98	18
valid_sources[0x0a]	56598	1			T96	3		T97	2		T98	10
valid_sources[0x0b]	56613	1			T96	1		T97	4		T98	15
valid_sources[0x0c]	57783	1			T98	40		T102	3		T155	16
valid_sources[0x0d]	56743	1			T96	3		T98	11		T155	9
valid_sources[0x0e]	55916	1			T96	5		T97	2		T98	23
valid_sources[0x0f]	56280	1			T96	4		T97	2		T98	33
valid_sources[0x10]	56677	1			T96	4		T97	1		T102	4
valid_sources[0x11]	57378	1			T96	3		T97	3		T98	32
valid_sources[0x12]	56838	1			T96	2		T97	2		T98	20
valid_sources[0x13]	56762	1			T96	2		T97	2		T98	10
valid_sources[0x14]	57221	1			T96	2		T97	3		T98	9
valid_sources[0x15]	56492	1			T96	6		T98	11		T102	2
valid_sources[0x16]	57742	1			T96	3		T97	4		T98	25
valid_sources[0x17]	56461	1			T96	5		T97	2		T98	2
valid_sources[0x18]	57331	1			T96	2		T97	1		T98	21
valid_sources[0x19]	57909	1			T96	4		T97	3		T98	10
valid_sources[0x1a]	56409	1			T96	4		T97	1		T98	6
valid_sources[0x1b]	57570	1			T96	3		T97	1		T98	49
valid_sources[0x1c]	57657	1			T96	1		T97	4		T98	20
valid_sources[0x1d]	56968	1			T96	1		T97	1		T98	11
valid_sources[0x1e]	57750	1			T96	3		T98	10		T102	3
valid_sources[0x1f]	57121	1			T96	3		T97	2		T98	23
valid_sources[0x20]	56339	1			T96	6		T97	2		T102	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53973

1

T96

4

T97

1

T98

19

values[0x0]

all_enables

biggest_size

401767

1

T96

26

T97

7

T98

165

values[0x1]

all_enables

biggest_size

54054

1

T96

2

T97

1

T98

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2967542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469238

1

T96

18

T97

32

T98

132

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1165006	1			T96	40		T97	39		T98	321
values[0x0]	1107113	1			T96	33		T97	51		T98	365
values[0x1]	1164661	1			T96	34		T97	50		T98	329

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2297188	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1139592

1

T96

46

T97

56

T98

334

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53950	1			T97	4		T98	25		T155	12
valid_sources[0x01]	54403	1			T96	1		T97	1		T98	27
valid_sources[0x02]	54185	1			T96	4		T98	14		T102	1
valid_sources[0x03]	54415	1			T96	1		T98	57		T102	3
valid_sources[0x04]	53859	1			T96	3		T97	14		T98	10
valid_sources[0x05]	52718	1			T96	3		T97	4		T98	25
valid_sources[0x06]	53032	1			T96	1		T98	31		T155	7
valid_sources[0x07]	53436	1			T96	7		T97	1		T98	7
valid_sources[0x08]	54197	1			T96	1		T97	2		T98	14
valid_sources[0x09]	53242	1			T96	2		T97	3		T98	22
valid_sources[0x0a]	53942	1			T96	2		T98	1		T102	1
valid_sources[0x0b]	54029	1			T96	5		T97	1		T102	3
valid_sources[0x0c]	53185	1			T96	2		T97	6		T98	13
valid_sources[0x0d]	54136	1			T96	1		T98	8		T155	9
valid_sources[0x0e]	53648	1			T98	17		T102	1		T155	9
valid_sources[0x0f]	53551	1			T96	1		T98	20		T155	12
valid_sources[0x10]	52891	1			T97	2		T98	9		T155	5
valid_sources[0x11]	54698	1			T96	1		T97	2		T98	14
valid_sources[0x12]	53498	1			T96	6		T97	5		T98	13
valid_sources[0x13]	53270	1			T96	1		T98	27		T102	1
valid_sources[0x14]	53097	1			T96	6		T97	7		T98	9
valid_sources[0x15]	53480	1			T98	8		T102	3		T155	12
valid_sources[0x16]	53798	1			T96	3		T97	3		T98	34
valid_sources[0x17]	53625	1			T98	26		T102	3		T155	6
valid_sources[0x18]	52974	1			T96	5		T97	4		T98	1
valid_sources[0x19]	53616	1			T97	1		T98	24		T102	4
valid_sources[0x1a]	53542	1			T97	1		T98	13		T102	2
valid_sources[0x1b]	53275	1			T96	1		T97	3		T98	24
valid_sources[0x1c]	53273	1			T97	6		T98	27		T102	1
valid_sources[0x1d]	53694	1			T97	7		T98	9		T102	3
valid_sources[0x1e]	53581	1			T96	7		T102	5		T155	9
valid_sources[0x1f]	53760	1			T96	1		T98	11		T155	17
valid_sources[0x20]	53569	1			T96	2		T98	11		T102	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49682

1

T96

2

T97

1

T98

11

values[0x0]

all_enables

biggest_size

369902

1

T96

15

T97

28

T98

108

values[0x1]

all_enables

biggest_size

49654

1

T96

1

T97

3

T98

13