Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.57			86.57

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_device	96.39			96.39

---

Module Instance : tb.dut.top_earlgrey.u_spi_device

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.39			96.39

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.39			96.39

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	65	50	76.92
Total Bits	432	374	86.57
Total Bits 0->1	216	187	86.57
Total Bits 1->0	216	187	86.57

Ports	65	50	76.92
Port Bits	432	374	86.57
Port Bits 0->1	216	187	86.57
Port Bits 1->0	216	187	86.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[12:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T37,*T100	Yes	T99,T37,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T100,T101	Yes	T37,T100,T101	INPUT
tl_i.a_valid	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	INPUT
tl_o.a_ready	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	OUTPUT
tl_o.d_error	Yes	Yes	T96,T98,T155	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T11,T12	Yes	T14,T11,T12	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T14,T11	Yes	T14,T11,T12	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T98,*T155,*T230	Yes	T96,T98,T102	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T14,*T11	Yes	T5,T14,T11	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T103,T104,T231	Yes	T103,T104,T231	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T103,T104,T231	Yes	T103,T104,T231	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	OUTPUT
cio_sck_i	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	INPUT
cio_csb_i	Yes	Yes	T13,T5,T26	Yes	T13,T11,T12	INPUT
cio_sd_o[3:0]	Yes	Yes	T11,T12,T22	Yes	T11,T12,T22	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T11,T22,T220	Yes	T11,T22,T220	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	INPUT
cio_tpm_csb_i	Yes	Yes	T14,T51,T52	Yes	T14,T51,T52	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T11,*T12,*T22	Yes	T11,T12,T22	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T13,T5,T26	Yes	T13,T11,T12	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T11,T220,T222	Yes	T11,T12,T22	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T13,T11	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T11,T124,T220	Yes	T11,T124,T220	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T14,T124,T51	Yes	T14,T124,T51	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.test	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.test	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.test	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.test	No	No		No		INPUT
sck_monitor_o	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_device

	Total	Covered	Percent
Totals	55	50	90.91
Total Bits	388	374	96.39
Total Bits 0->1	194	187	96.39
Total Bits 1->0	194	187	96.39

Ports	55	50	90.91
Port Bits	388	374	96.39
Port Bits 0->1	194	187	96.39
Port Bits 1->0	194	187	96.39

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[12:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T37,*T100	Yes	T99,T37,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T100,T101	Yes	T37,T100,T101	INPUT
tl_i.a_valid	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	INPUT
tl_o.a_ready	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	OUTPUT
tl_o.d_error	Yes	Yes	T96,T98,T155	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T11,T12	Yes	T14,T11,T12	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T14,T11	Yes	T14,T11,T12	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T98,*T155,*T230	Yes	T96,T98,T102	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T14,*T11	Yes	T5,T14,T11	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T14,T11	Yes	T5,T14,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T103,T104,T231	Yes	T103,T104,T231	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T103,T104,T231	Yes	T103,T104,T231	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	OUTPUT
cio_sck_i	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	INPUT
cio_csb_i	Yes	Yes	T13,T5,T26	Yes	T13,T11,T12	INPUT
cio_sd_o[3:0]	Yes	Yes	T11,T12,T22	Yes	T11,T12,T22	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T11,T22,T220	Yes	T11,T22,T220	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	INPUT
cio_tpm_csb_i	Yes	Yes	T14,T51,T52	Yes	T14,T51,T52	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T11,*T12,*T22	Yes	T11,T12,T22	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	OUTPUT
passthrough_o.csb_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.csb	Yes	Yes	T13,T5,T26	Yes	T13,T11,T12	OUTPUT
passthrough_o.sck_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.sck	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T11,T220,T222	Yes	T11,T12,T22	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T13,T11	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T11,T124,T220	Yes	T11,T124,T220	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T14,T124,T51	Yes	T14,T124,T51	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T124,T184,T185	Yes	T124,T184,T185	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.test	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.test	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.test	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.test	No	No		No		INPUT
sck_monitor_o	Yes	Yes	T5,T14,T11	Yes	T13,T5,T14	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range