SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_prim_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_trst_n |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tms |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tdi |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tdo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tdo_oe |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_trst_n |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tms |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tdi |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tdo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tdo_oe |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_trst_n |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tms |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tdi |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tdo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_buf_tdo_oe |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_prim_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_secure_anchor_buf |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T32 T33 T58 16 1/1 assign out_o = ~inv; Tests: T32 T33 T58
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T32 T33 T58 16 1/1 assign out_o = ~inv; Tests: T32 T33 T58
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T32 T33 T58 16 1/1 assign out_o = ~inv; Tests: T32 T33 T58
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T32 T33 T58 16 1/1 assign out_o = ~inv; Tests: T32 T33 T58
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T44 T45 T32 16 1/1 assign out_o = ~inv; Tests: T44 T45 T32
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T44 T45 T32 16 1/1 assign out_o = ~inv; Tests: T44 T45 T32
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T44 T45 T32 16 1/1 assign out_o = ~inv; Tests: T44 T45 T32
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T44 T45 T32 16 1/1 assign out_o = ~inv; Tests: T44 T45 T32
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3 16 1/1 assign out_o = ~inv; Tests: T1 T2 T3
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T36 T32 T33 16 1/1 assign out_o = ~inv; Tests: T36 T32 T33
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T36 T32 T33 16 1/1 assign out_o = ~inv; Tests: T36 T32 T33
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T36 T32 T33 16 1/1 assign out_o = ~inv; Tests: T36 T32 T33
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T36 T32 T33 16 1/1 assign out_o = ~inv; Tests: T36 T32 T33
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T36 T32 T33 16 1/1 assign out_o = ~inv; Tests: T36 T32 T33
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T86 T88 T89 16 1/1 assign out_o = ~inv; Tests: T86 T88 T89
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T86 T88 T89 16 1/1 assign out_o = ~inv; Tests: T86 T88 T89
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T86 T88 T89 16 1/1 assign out_o = ~inv; Tests: T86 T88 T89
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T86 T88 T89 16 1/1 assign out_o = ~inv; Tests: T86 T88 T89
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T86 T88 T89 16 1/1 assign out_o = ~inv; Tests: T86 T88 T89
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T85 T86 T91 16 1/1 assign out_o = ~inv; Tests: T85 T86 T91
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T85 T86 T91 16 1/1 assign out_o = ~inv; Tests: T85 T86 T91
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T85 T86 T91 16 1/1 assign out_o = ~inv; Tests: T85 T86 T91
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T85 T86 T92 16 1/1 assign out_o = ~inv; Tests: T85 T86 T92
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T85 T86 T92 16 1/1 assign out_o = ~inv; Tests: T85 T86 T92
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T78 T171 T157 16 1/1 assign out_o = ~inv; Tests: T78 T171 T157
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T158 T376 16 1/1 assign out_o = ~inv; Tests: T157 T158 T376
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T158 T170 16 1/1 assign out_o = ~inv; Tests: T157 T158 T170
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T160 T161 16 1/1 assign out_o = ~inv; Tests: T157 T160 T161
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T158 T160 16 1/1 assign out_o = ~inv; Tests: T157 T158 T160
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T160 T161 16 1/1 assign out_o = ~inv; Tests: T157 T160 T161
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T158 T160 16 1/1 assign out_o = ~inv; Tests: T157 T158 T160
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T160 T161 16 1/1 assign out_o = ~inv; Tests: T157 T160 T161
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T160 T165 16 1/1 assign out_o = ~inv; Tests: T157 T160 T165
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T160 T137 16 1/1 assign out_o = ~inv; Tests: T157 T160 T137
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T160 T137 16 1/1 assign out_o = ~inv; Tests: T157 T160 T137
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T160 T161 16 1/1 assign out_o = ~inv; Tests: T157 T160 T161
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 15 | 1 | 1 | 100.00 |
CONT_ASSIGN | 16 | 1 | 1 | 100.00 |
14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T157 T160 T161 16 1/1 assign out_o = ~inv; Tests: T157 T160 T161
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |