Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
256 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
256 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
256 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
256 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
247 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
247 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
247 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
247 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
212 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
212 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
212 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
212 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
264 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
264 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
264 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
264 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
244 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
244 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T69 T163 T384
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T69,T163,T384 |
| 1 | 1 | Covered | T175,T420,T457 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T69,T163,T384 |
| 1 | 0 | Covered | T175,T420,T457 |
| 1 | 1 | Covered | T69,T163,T384 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
244 |
0 |
0 |
| T69 |
410442 |
1 |
0 |
0 |
| T127 |
112592 |
0 |
0 |
0 |
| T162 |
64775 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
42524 |
0 |
0 |
0 |
| T424 |
58647 |
0 |
0 |
0 |
| T425 |
57582 |
0 |
0 |
0 |
| T426 |
34466 |
0 |
0 |
0 |
| T427 |
53904 |
0 |
0 |
0 |
| T428 |
59309 |
0 |
0 |
0 |
| T429 |
70241 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
244 |
0 |
0 |
| T69 |
3755 |
1 |
0 |
0 |
| T127 |
1036 |
0 |
0 |
0 |
| T162 |
795 |
0 |
0 |
0 |
| T174 |
0 |
1 |
0 |
0 |
| T175 |
0 |
2 |
0 |
0 |
| T384 |
0 |
1 |
0 |
0 |
| T407 |
0 |
1 |
0 |
0 |
| T417 |
0 |
2 |
0 |
0 |
| T419 |
0 |
1 |
0 |
0 |
| T420 |
0 |
2 |
0 |
0 |
| T421 |
0 |
2 |
0 |
0 |
| T422 |
0 |
1 |
0 |
0 |
| T423 |
583 |
0 |
0 |
0 |
| T424 |
774 |
0 |
0 |
0 |
| T425 |
739 |
0 |
0 |
0 |
| T426 |
1158 |
0 |
0 |
0 |
| T427 |
640 |
0 |
0 |
0 |
| T428 |
750 |
0 |
0 |
0 |
| T429 |
918 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T5 T29 T76
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T5,T29,T76 |
| 1 | 0 | Covered | T5,T29,T76 |
| 1 | 1 | Covered | T5,T76,T77 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T5,T29,T76 |
| 1 | 0 | Covered | T5,T76,T77 |
| 1 | 1 | Covered | T5,T29,T76 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683357 |
277 |
0 |
0 |
| T5 |
558 |
3 |
0 |
0 |
| T6 |
382 |
0 |
0 |
0 |
| T14 |
499 |
0 |
0 |
0 |
| T26 |
939 |
0 |
0 |
0 |
| T29 |
490 |
0 |
0 |
0 |
| T34 |
457 |
0 |
0 |
0 |
| T36 |
341 |
0 |
0 |
0 |
| T44 |
704 |
0 |
0 |
0 |
| T72 |
717 |
0 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
2 |
0 |
0 |
| T81 |
0 |
1 |
0 |
0 |
| T82 |
0 |
3 |
0 |
0 |
| T83 |
0 |
3 |
0 |
0 |
| T94 |
0 |
4 |
0 |
0 |
| T107 |
353 |
0 |
0 |
0 |
| T121 |
0 |
2 |
0 |
0 |
| T418 |
0 |
4 |
0 |
0 |
| T432 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
145398904 |
280 |
0 |
0 |
| T5 |
35865 |
3 |
0 |
0 |
| T6 |
24364 |
0 |
0 |
0 |
| T14 |
38050 |
0 |
0 |
0 |
| T26 |
31929 |
0 |
0 |
0 |
| T29 |
25131 |
1 |
0 |
0 |
| T34 |
22353 |
0 |
0 |
0 |
| T36 |
19347 |
0 |
0 |
0 |
| T44 |
59886 |
0 |
0 |
0 |
| T72 |
51087 |
0 |
0 |
0 |
| T75 |
0 |
1 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
2 |
0 |
0 |
| T81 |
0 |
2 |
0 |
0 |
| T82 |
0 |
3 |
0 |
0 |
| T94 |
0 |
4 |
0 |
0 |
| T107 |
20852 |
0 |
0 |
0 |
| T121 |
0 |
2 |
0 |
0 |
| T418 |
0 |
4 |
0 |
0 |