Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490765166	58735519	0	0
DepthKnown_A	490765166	490661446	0	0
RvalidKnown_A	490765166	490661446	0	0
WreadyKnown_A	490765166	490661446	0	0
gen_passthru_fifo.paramCheckPass	1015	1015	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	58735519	0	0
T1	42241	3485	0	0
T2	65307	7637	0	0
T3	76232	7709	0	0
T4	83391	10449	0	0
T5	102036	13577	0	0
T7	82758	9006	0	0
T10	110267	13574	0	0
T13	86437	9148	0	0
T106	87384	9175	0	0
T107	82198	10421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015	1015	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490765166	44086264	0	0
DepthKnown_A	490765166	490661446	0	0
RvalidKnown_A	490765166	490661446	0	0
WreadyKnown_A	490765166	490661446	0	0
gen_passthru_fifo.paramCheckPass	1015	1015	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	44086264	0	0
T1	42241	1880	0	0
T2	65307	5106	0	0
T3	76232	6052	0	0
T4	83391	7615	0	0
T5	102036	9363	0	0
T7	82758	6634	0	0
T10	110267	10791	0	0
T13	86437	6573	0	0
T106	87384	7516	0	0
T107	82198	7424	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015	1015	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490765166	42084954	0	0
DepthKnown_A	490765166	490661446	0	0
RvalidKnown_A	490765166	490661446	0	0
WreadyKnown_A	490765166	490661446	0	0
gen_passthru_fifo.paramCheckPass	1015	1015	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	42084954	0	0
T1	42241	461	0	0
T2	65307	4869	0	0
T3	76232	4796	0	0
T4	83391	5389	0	0
T5	102036	6250	0	0
T7	82758	4041	0	0
T10	110267	7751	0	0
T13	86437	7165	0	0
T106	87384	5860	0	0
T107	82198	6953	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015	1015	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T37 T100 T101 
49         1/1              assign full_o = rready_i;
           Tests:       T37 T100 T101 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490765166	35058113	0	0
DepthKnown_A	490765166	490661446	0	0
RvalidKnown_A	490765166	490661446	0	0
WreadyKnown_A	490765166	490661446	0	0
gen_passthru_fifo.paramCheckPass	1015	1015	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	35058113	0	0
T1	42241	353	0	0
T2	65307	4693	0	0
T3	76232	4682	0	0
T4	83391	5219	0	0
T5	102036	6008	0	0
T7	82758	3908	0	0
T10	110267	7579	0	0
T13	86437	6708	0	0
T106	87384	5746	0	0
T107	82198	6358	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490765166	490661446	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015	1015	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577903470	89811	0	0
DepthKnown_A	577903470	577783319	0	0
RvalidKnown_A	577903470	577783319	0	0
WreadyKnown_A	577903470	577783319	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	89811	0	0
T1	42241	8	0	0
T2	65307	24	0	0
T3	76232	13	0	0
T4	83391	24	0	0
T5	102036	25	0	0
T7	82758	13	0	0
T10	110267	18	0	0
T13	86437	208	0	0
T106	87384	13	0	0
T107	82198	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577903470	93286	0	0
DepthKnown_A	577903470	577783319	0	0
RvalidKnown_A	577903470	577783319	0	0
WreadyKnown_A	577903470	577783319	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	93286	0	0
T1	42241	8	0	0
T2	65307	24	0	0
T3	76232	13	0	0
T4	83391	24	0	0
T5	102036	25	0	0
T7	82758	13	0	0
T10	110267	18	0	0
T13	86437	208	0	0
T106	87384	13	0	0
T107	82198	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577903470	51128	0	0
DepthKnown_A	577903470	577783319	0	0
RvalidKnown_A	577903470	577783319	0	0
WreadyKnown_A	577903470	577783319	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	51128	0	0
T1	42241	8	0	0
T2	65307	23	0	0
T3	76232	12	0	0
T4	83391	21	0	0
T5	102036	22	0	0
T7	82758	12	0	0
T10	110267	15	0	0
T13	86437	205	0	0
T106	87384	12	0	0
T107	82198	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577903470	51129	0	0
DepthKnown_A	577903470	577783319	0	0
RvalidKnown_A	577903470	577783319	0	0
WreadyKnown_A	577903470	577783319	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	51129	0	0
T1	42241	8	0	0
T2	65307	23	0	0
T3	76232	12	0	0
T4	83391	21	0	0
T5	102036	22	0	0
T7	82758	12	0	0
T10	110267	15	0	0
T13	86437	205	0	0
T106	87384	12	0	0
T107	82198	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577903470	38683	0	0
DepthKnown_A	577903470	577783319	0	0
RvalidKnown_A	577903470	577783319	0	0
WreadyKnown_A	577903470	577783319	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	38683	0	0
T2	65307	1	0	0
T3	76232	1	0	0
T4	83391	3	0	0
T5	102036	3	0	0
T6	96790	3	0	0
T7	82758	1	0	0
T10	110267	3	0	0
T13	86437	3	0	0
T106	87384	1	0	0
T107	82198	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577903470	42157	0	0
DepthKnown_A	577903470	577783319	0	0
RvalidKnown_A	577903470	577783319	0	0
WreadyKnown_A	577903470	577783319	0	0
gen_passthru_fifo.paramCheckPass	2926	2926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	42157	0	0
T2	65307	1	0	0
T3	76232	1	0	0
T4	83391	3	0	0
T5	102036	3	0	0
T6	96790	3	0	0
T7	82758	1	0	0
T10	110267	3	0	0
T13	86437	3	0	0
T106	87384	1	0	0
T107	82198	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577903470	577783319	0	0
T1	42241	42179	0	0
T2	65307	65249	0	0
T3	76232	76181	0	0
T4	83391	83329	0	0
T5	102036	101981	0	0
T7	82758	82696	0	0
T10	110267	110216	0	0
T13	86437	86382	0	0
T106	87384	87322	0	0
T107	82198	82147	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2926	2926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T106	1	1	0	0
T107	1	1	0	0