Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T37,*T100	Yes	T99,T37,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T100,T101	Yes	T37,T100,T101	INPUT
tl_i.a_valid	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	INPUT
tl_o.a_ready	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
tl_o.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T57,*T271,*T96	Yes	T57,T271,T96	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T72,*T128,*T65	Yes	T72,T128,T65	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	OUTPUT
cio_rx_i	Yes	Yes	T13,T72,T44	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
intr_tx_empty_o	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
intr_rx_watermark_o	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
intr_tx_done_o	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
intr_rx_overflow_o	Yes	Yes	T72,T128,T65	Yes	T72,T128,T65	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T72,T219,T309	Yes	T72,T219,T309	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T72,T219,T309	Yes	T72,T219,T309	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T37,*T100	Yes	T99,T37,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T100,T101	Yes	T37,T100,T101	INPUT
tl_i.a_valid	Yes	Yes	T72,T78,T219	Yes	T72,T78,T219	INPUT
tl_o.a_ready	Yes	Yes	T72,T78,T267	Yes	T72,T78,T267	OUTPUT
tl_o.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T72,T309,T314	Yes	T72,T309,T314	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T72,T267,T309	Yes	T72,T78,T267	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T72,T267,T309	Yes	T72,T78,T267	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T98,T102	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T57,*T271,*T96	Yes	T57,T271,T96	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T72,*T309,*T314	Yes	T72,T309,T314	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T72,T78,T267	Yes	T72,T78,T267	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	OUTPUT
cio_rx_i	Yes	Yes	T13,T72,T44	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T72,T56,T53	Yes	T72,T56,T53	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T72,T309,T314	Yes	T72,T309,T314	OUTPUT
intr_tx_empty_o	Yes	Yes	T72,T309,T315	Yes	T72,T309,T315	OUTPUT
intr_rx_watermark_o	Yes	Yes	T72,T309,T315	Yes	T72,T309,T315	OUTPUT
intr_tx_done_o	Yes	Yes	T72,T309,T316	Yes	T72,T309,T316	OUTPUT
intr_rx_overflow_o	Yes	Yes	T72,T309,T316	Yes	T72,T309,T316	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T128,T309,T22	Yes	T128,T309,T22	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T128,T309,T22	Yes	T128,T309,T22	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T37,*T100	Yes	T99,T37,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T100,T101	Yes	T37,T100,T101	INPUT
tl_i.a_valid	Yes	Yes	T128,T78,T267	Yes	T128,T78,T267	INPUT
tl_o.a_ready	Yes	Yes	T128,T78,T267	Yes	T128,T78,T267	OUTPUT
tl_o.d_error	Yes	Yes	T97,T98,T102	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T128,T309,T22	Yes	T128,T309,T22	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T128,T267,T309	Yes	T128,T78,T267	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T128,T267,T309	Yes	T128,T78,T267	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T98,*T102,*T155	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T128,*T309,*T22	Yes	T128,T309,T22	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T128,T78,T267	Yes	T128,T78,T267	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	OUTPUT
cio_rx_i	Yes	Yes	T128,T47,T129	Yes	T10,T13,T128	INPUT
cio_tx_o	Yes	Yes	T128,T129,T130	Yes	T128,T129,T130	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T128,T309,T129	Yes	T128,T309,T129	OUTPUT
intr_tx_empty_o	Yes	Yes	T128,T309,T129	Yes	T128,T309,T129	OUTPUT
intr_rx_watermark_o	Yes	Yes	T128,T309,T129	Yes	T128,T309,T129	OUTPUT
intr_tx_done_o	Yes	Yes	T128,T309,T129	Yes	T128,T309,T129	OUTPUT
intr_rx_overflow_o	Yes	Yes	T128,T309,T129	Yes	T128,T309,T129	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T65,T66,T309	Yes	T65,T66,T309	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T65,T66,T309	Yes	T65,T66,T309	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T37,*T100	Yes	T99,T37,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T100,T101	Yes	T37,T100,T101	INPUT
tl_i.a_valid	Yes	Yes	T65,T66,T78	Yes	T65,T66,T78	INPUT
tl_o.a_ready	Yes	Yes	T65,T66,T78	Yes	T65,T66,T78	OUTPUT
tl_o.d_error	Yes	Yes	T97,T98,T102	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T65,T66,T309	Yes	T65,T66,T309	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T66,T267	Yes	T65,T66,T78	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T65,T66,T267	Yes	T65,T66,T78	OUTPUT
tl_o.d_sink	Yes	Yes	T97,T98,T102	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T97,*T98,*T155	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T65,*T66,*T309	Yes	T65,T66,T309	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T65,T66,T78	Yes	T65,T66,T78	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	OUTPUT
cio_rx_i	Yes	Yes	T65,T66,T131	Yes	T65,T66,T131	INPUT
cio_tx_o	Yes	Yes	T65,T66,T131	Yes	T65,T66,T131	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T65,T66,T309	Yes	T65,T66,T309	OUTPUT
intr_tx_empty_o	Yes	Yes	T65,T66,T309	Yes	T65,T66,T309	OUTPUT
intr_rx_watermark_o	Yes	Yes	T65,T66,T309	Yes	T65,T66,T309	OUTPUT
intr_tx_done_o	Yes	Yes	T65,T66,T309	Yes	T65,T66,T309	OUTPUT
intr_rx_overflow_o	Yes	Yes	T65,T66,T309	Yes	T65,T66,T309	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T37,*T100	Yes	T99,T37,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T37,T100,T101	Yes	T37,T100,T101	INPUT
tl_i.a_valid	Yes	Yes	T39,T78,T67	Yes	T39,T78,T67	INPUT
tl_o.a_ready	Yes	Yes	T39,T78,T67	Yes	T39,T78,T67	OUTPUT
tl_o.d_error	Yes	Yes	T96,T98,T155	Yes	T96,T98,T155	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T39,T67,T68	Yes	T39,T78,T67	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T39,T67,T68	Yes	T39,T78,T67	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T98,*T155,*T230	Yes	T97,T98,T102	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T97,T98,T102	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T39,*T67,*T68	Yes	T39,T67,T68	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T78,T67	Yes	T39,T78,T67	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T103,T104	Yes	T78,T103,T104	OUTPUT
cio_rx_i	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	INPUT
cio_tx_o	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	OUTPUT
intr_tx_empty_o	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	OUTPUT
intr_rx_watermark_o	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	OUTPUT
intr_tx_done_o	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	OUTPUT
intr_rx_overflow_o	Yes	Yes	T39,T67,T68	Yes	T39,T67,T68	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T317,T318	Yes	T309,T317,T318	OUTPUT

*Tests covering at least one bit in the range