Line Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 36 | 36 | 100.00 |
| CONT_ASSIGN | 55 | 0 | 0 | |
| CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
| ALWAYS | 219 | 12 | 12 | 100.00 |
| ALWAYS | 263 | 12 | 12 | 100.00 |
| ALWAYS | 307 | 5 | 5 | 100.00 |
| ALWAYS | 316 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 335 | 0 | 0 | |
| ALWAYS | 339 | 0 | 0 | |
54 logic unused_req_chk;
55 unreachable assign unused_req_chk = req_chk_i;
56
57 if (EnRzHs) begin : gen_rz_hs_protocol
58 //////////////////
59 // RZ protocol //
60 //////////////////
61
62 // Types
63 typedef enum logic {
64 LoSt, HiSt
65 } rz_fsm_e;
66
67 // Signals
68 rz_fsm_e src_fsm_d, src_fsm_q;
69 rz_fsm_e dst_fsm_d, dst_fsm_q;
70 logic src_ack, dst_ack;
71 logic src_req, dst_req;
72
73 // REQ-side FSM (SRC domain)
74 always_comb begin : src_fsm
75 src_fsm_d = src_fsm_q;
76 src_ack_o = 1'b0;
77 src_req = 1'b0;
78
79 unique case (src_fsm_q)
80 LoSt: begin
81 // Wait for the ack to go back to zero before starting
82 // a new transaction.
83 if (!src_ack && src_req_i) begin
84 src_fsm_d = HiSt;
85 end
86 end
87 HiSt: begin
88 src_req = 1'b1;
89 // Forward the acknowledgement.
90 src_ack_o = src_ack;
91 // If request drops out, we go back to LoSt.
92 // If DST side asserts ack, we also go back to LoSt.
93 if (!src_req_i || src_ack) begin
94 src_fsm_d = LoSt;
95 end
96 end
97 //VCS coverage off
98 // pragma coverage off
99 default: ;
100 //VCS coverage on
101 // pragma coverage on
102 endcase
103 end
104
105 // Move ACK over to SRC domain.
106 prim_flop_2sync #(
107 .Width(1)
108 ) ack_sync (
109 .clk_i (clk_src_i),
110 .rst_ni (rst_src_ni),
111 .d_i (dst_ack),
112 .q_o (src_ack)
113 );
114
115 // Registers
116 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
117 if (!rst_src_ni) begin
118 src_fsm_q <= LoSt;
119 end else begin
120 src_fsm_q <= src_fsm_d;
121 end
122 end
123
124 // ACK-side FSM (DST domain)
125 always_comb begin : dst_fsm
126 dst_fsm_d = dst_fsm_q;
127 dst_req_o = 1'b0;
128 dst_ack = 1'b0;
129
130 unique case (dst_fsm_q)
131 LoSt: begin
132 if (dst_req) begin
133 // Forward the request.
134 dst_req_o = 1'b1;
135 // Wait for the request and acknowledge to be asserted
136 // before responding to the SRC side.
137 if (dst_ack_i) begin
138 dst_fsm_d = HiSt;
139 end
140 end
141 end
142 HiSt: begin
143 dst_ack = 1'b1;
144 // Wait for the request to drop back to zero.
145 if (!dst_req) begin
146 dst_fsm_d = LoSt;
147 end
148 end
149 //VCS coverage off
150 // pragma coverage off
151 default: ;
152 //VCS coverage on
153 // pragma coverage on
154 endcase
155 end
156
157 // Move REQ over to DST domain.
158 prim_flop_2sync #(
159 .Width(1)
160 ) req_sync (
161 .clk_i (clk_dst_i),
162 .rst_ni (rst_dst_ni),
163 .d_i (src_req),
164 .q_o (dst_req)
165 );
166
167 // Registers
168 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
169 if (!rst_dst_ni) begin
170 dst_fsm_q <= LoSt;
171 end else begin
172 dst_fsm_q <= dst_fsm_d;
173 end
174 end
175
176 end else begin : gen_nrz_hs_protocol
177 //////////////////
178 // NRZ protocol //
179 //////////////////
180
181 // Types
182 typedef enum logic {
183 EVEN, ODD
184 } sync_reqack_fsm_e;
185
186 // Signals
187 sync_reqack_fsm_e src_fsm_ns, src_fsm_cs;
188 sync_reqack_fsm_e dst_fsm_ns, dst_fsm_cs;
189
190 logic src_req_d, src_req_q, src_ack;
191 logic dst_ack_d, dst_ack_q, dst_req;
192 logic src_handshake, dst_handshake;
193
194 1/1 assign src_handshake = src_req_i & src_ack_o;
Tests: T2 T3 T5
195 1/1 assign dst_handshake = dst_req_o & dst_ack_i;
Tests: T1 T2 T5
196
197 // Move REQ over to DST domain.
198 prim_flop_2sync #(
199 .Width(1)
200 ) req_sync (
201 .clk_i (clk_dst_i),
202 .rst_ni (rst_dst_ni),
203 .d_i (src_req_q),
204 .q_o (dst_req)
205 );
206
207 // Move ACK over to SRC domain.
208 prim_flop_2sync #(
209 .Width(1)
210 ) ack_sync (
211 .clk_i (clk_src_i),
212 .rst_ni (rst_src_ni),
213 .d_i (dst_ack_q),
214 .q_o (src_ack)
215 );
216
217 // REQ-side FSM (SRC domain)
218 always_comb begin : src_fsm
219 1/1 src_fsm_ns = src_fsm_cs;
Tests: T1 T2 T5
220
221 // By default, we keep the internal REQ value and don't ACK.
222 1/1 src_req_d = src_req_q;
Tests: T1 T2 T5
223 1/1 src_ack_o = 1'b0;
Tests: T1 T2 T5
224
225 1/1 unique case (src_fsm_cs)
Tests: T1 T2 T5
226
227 EVEN: begin
228 // Simply forward REQ and ACK.
229 1/1 src_req_d = src_req_i;
Tests: T1 T2 T5
230 1/1 src_ack_o = src_ack;
Tests: T1 T2 T5
231
232 // The handshake is done for exactly 1 clock cycle.
233 1/1 if (src_handshake) begin
Tests: T1 T2 T5
234 1/1 src_fsm_ns = ODD;
Tests: T2 T3 T4
235 end
MISSING_ELSE
236 end
237
238 ODD: begin
239 // Internal REQ and ACK have inverted meaning now. If src_req_i is high again, this
240 // signals a new transaction.
241 1/1 src_req_d = ~src_req_i;
Tests: T2 T3 T4
242 1/1 src_ack_o = ~src_ack;
Tests: T2 T3 T4
243
244 // The handshake is done for exactly 1 clock cycle.
245 1/1 if (src_handshake) begin
Tests: T2 T3 T4
246 1/1 src_fsm_ns = EVEN;
Tests: T4 T10 T13
247 end
MISSING_ELSE
248 end
249
250 //VCS coverage off
251 // pragma coverage off
252
253 default: ;
254
255 //VCS coverage on
256 // pragma coverage on
257
258 endcase
259 end
260
261 // ACK-side FSM (DST domain)
262 always_comb begin : dst_fsm
263 1/1 dst_fsm_ns = dst_fsm_cs;
Tests: T1 T2 T5
264
265 // By default, we don't REQ and keep the internal ACK.
266 1/1 dst_req_o = 1'b0;
Tests: T1 T2 T5
267 1/1 dst_ack_d = dst_ack_q;
Tests: T1 T2 T5
268
269 1/1 unique case (dst_fsm_cs)
Tests: T1 T2 T5
270
271 EVEN: begin
272 // Simply forward REQ and ACK.
273 1/1 dst_req_o = dst_req;
Tests: T1 T2 T5
274 1/1 dst_ack_d = dst_ack_i;
Tests: T1 T2 T5
275
276 // The handshake is done for exactly 1 clock cycle.
277 1/1 if (dst_handshake) begin
Tests: T1 T2 T5
278 1/1 dst_fsm_ns = ODD;
Tests: T2 T3 T4
279 end
MISSING_ELSE
280 end
281
282 ODD: begin
283 // Internal REQ and ACK have inverted meaning now. If dst_req goes low, this signals a new
284 // transaction.
285 1/1 dst_req_o = ~dst_req;
Tests: T2 T3 T4
286 1/1 dst_ack_d = ~dst_ack_i;
Tests: T2 T3 T4
287
288 // The handshake is done for exactly 1 clock cycle.
289 1/1 if (dst_handshake) begin
Tests: T2 T3 T4
290 1/1 dst_fsm_ns = EVEN;
Tests: T4 T10 T13
291 end
MISSING_ELSE
292 end
293
294 //VCS coverage off
295 // pragma coverage off
296
297 default: ;
298
299 //VCS coverage on
300 // pragma coverage on
301
302 endcase
303 end
304
305 // Registers
306 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
307 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
308 1/1 src_fsm_cs <= EVEN;
Tests: T1 T2 T3
309 1/1 src_req_q <= 1'b0;
Tests: T1 T2 T3
310 end else begin
311 1/1 src_fsm_cs <= src_fsm_ns;
Tests: T1 T2 T3
312 1/1 src_req_q <= src_req_d;
Tests: T1 T2 T3
313 end
314 end
315 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
316 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
317 1/1 dst_fsm_cs <= EVEN;
Tests: T1 T2 T3
318 1/1 dst_ack_q <= 1'b0;
Tests: T1 T2 T3
319 end else begin
320 1/1 dst_fsm_cs <= dst_fsm_ns;
Tests: T1 T2 T3
321 1/1 dst_ack_q <= dst_ack_d;
Tests: T1 T2 T3
322 end
323 end
324 end
325
326 ////////////////
327 // Assertions //
328 ////////////////
329
330 `ifdef INC_ASSERT
331 //VCS coverage off
332 // pragma coverage off
333
334 logic effective_rst_n;
335 unreachable assign effective_rst_n = rst_src_ni && rst_dst_ni;
336
337 logic chk_flag;
338 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
339 unreachable if (!effective_rst_n) begin
340 unreachable chk_flag <= '0;
341 unreachable end else if (src_req_i && !chk_flag) begin
342 unreachable chk_flag <= 1'b1;
343 end
==> MISSING_ELSE
Cond Coverage for Module :
prim_sync_reqack
| Total | Covered | Percent |
|---|
| Conditions | 6 | 4 | 66.67 |
| Logical | 6 | 4 | 66.67 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
| Branches |
|
12 |
12 |
100.00 |
| CASE |
225 |
4 |
4 |
100.00 |
| CASE |
269 |
4 |
4 |
100.00 |
| IF |
307 |
2 |
2 |
100.00 |
| IF |
316 |
2 |
2 |
100.00 |
225 unique case (src_fsm_cs)
-1-
226
227 EVEN: begin
228 // Simply forward REQ and ACK.
229 src_req_d = src_req_i;
230 src_ack_o = src_ack;
231
232 // The handshake is done for exactly 1 clock cycle.
233 if (src_handshake) begin
-2-
234 src_fsm_ns = ODD;
==>
235 end
MISSING_ELSE
==>
236 end
237
238 ODD: begin
239 // Internal REQ and ACK have inverted meaning now. If src_req_i is high again, this
240 // signals a new transaction.
241 src_req_d = ~src_req_i;
242 src_ack_o = ~src_ack;
243
244 // The handshake is done for exactly 1 clock cycle.
245 if (src_handshake) begin
-3-
246 src_fsm_ns = EVEN;
==>
247 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| EVEN |
1 |
- |
Covered |
T2,T3,T4 |
| EVEN |
0 |
- |
Covered |
T1,T2,T5 |
| ODD |
- |
1 |
Covered |
T4,T10,T13 |
| ODD |
- |
0 |
Covered |
T2,T3,T4 |
269 unique case (dst_fsm_cs)
-1-
270
271 EVEN: begin
272 // Simply forward REQ and ACK.
273 dst_req_o = dst_req;
274 dst_ack_d = dst_ack_i;
275
276 // The handshake is done for exactly 1 clock cycle.
277 if (dst_handshake) begin
-2-
278 dst_fsm_ns = ODD;
==>
279 end
MISSING_ELSE
==>
280 end
281
282 ODD: begin
283 // Internal REQ and ACK have inverted meaning now. If dst_req goes low, this signals a new
284 // transaction.
285 dst_req_o = ~dst_req;
286 dst_ack_d = ~dst_ack_i;
287
288 // The handshake is done for exactly 1 clock cycle.
289 if (dst_handshake) begin
-3-
290 dst_fsm_ns = EVEN;
==>
291 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| EVEN |
1 |
- |
Covered |
T2,T3,T4 |
| EVEN |
0 |
- |
Covered |
T1,T2,T5 |
| ODD |
- |
1 |
Covered |
T4,T10,T13 |
| ODD |
- |
0 |
Covered |
T2,T3,T4 |
307 if (!rst_src_ni) begin
-1-
308 src_fsm_cs <= EVEN;
==>
309 src_req_q <= 1'b0;
310 end else begin
311 src_fsm_cs <= src_fsm_ns;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
316 if (!rst_dst_ni) begin
-1-
317 dst_fsm_cs <= EVEN;
==>
318 dst_ack_q <= 1'b0;
319 end else begin
320 dst_fsm_cs <= dst_fsm_ns;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
758431426 |
4608 |
0 |
0 |
| T2 |
65307 |
1 |
0 |
0 |
| T3 |
76232 |
1 |
0 |
0 |
| T4 |
83391 |
2 |
0 |
0 |
| T5 |
137901 |
8 |
0 |
0 |
| T6 |
121154 |
2 |
0 |
0 |
| T7 |
82758 |
1 |
0 |
0 |
| T10 |
110267 |
2 |
0 |
0 |
| T13 |
86437 |
2 |
0 |
0 |
| T14 |
38050 |
0 |
0 |
0 |
| T26 |
31929 |
1 |
0 |
0 |
| T27 |
0 |
1 |
0 |
0 |
| T29 |
25131 |
2 |
0 |
0 |
| T34 |
22353 |
0 |
0 |
0 |
| T36 |
19347 |
0 |
0 |
0 |
| T44 |
59886 |
0 |
0 |
0 |
| T72 |
51087 |
0 |
0 |
0 |
| T75 |
0 |
2 |
0 |
0 |
| T76 |
33518 |
3 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T82 |
0 |
6 |
0 |
0 |
| T88 |
39928 |
0 |
0 |
0 |
| T94 |
0 |
6 |
0 |
0 |
| T106 |
87384 |
1 |
0 |
0 |
| T107 |
103050 |
1 |
0 |
0 |
| T121 |
0 |
3 |
0 |
0 |
| T205 |
21497 |
8 |
0 |
0 |
| T206 |
0 |
8 |
0 |
0 |
| T295 |
49031 |
0 |
0 |
0 |
SyncReqAckHoldReq
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
983213689 |
4462 |
0 |
0 |
| T2 |
65307 |
1 |
0 |
0 |
| T3 |
76232 |
1 |
0 |
0 |
| T4 |
83391 |
2 |
0 |
0 |
| T5 |
102594 |
7 |
0 |
0 |
| T6 |
97172 |
2 |
0 |
0 |
| T7 |
82758 |
1 |
0 |
0 |
| T10 |
110267 |
2 |
0 |
0 |
| T13 |
86437 |
2 |
0 |
0 |
| T14 |
499 |
0 |
0 |
0 |
| T26 |
939 |
1 |
0 |
0 |
| T27 |
0 |
1 |
0 |
0 |
| T29 |
490 |
1 |
0 |
0 |
| T34 |
457 |
0 |
0 |
0 |
| T36 |
341 |
0 |
0 |
0 |
| T44 |
704 |
0 |
0 |
0 |
| T72 |
717 |
0 |
0 |
0 |
| T75 |
0 |
1 |
0 |
0 |
| T76 |
138074 |
3 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T82 |
0 |
5 |
0 |
0 |
| T88 |
163199 |
0 |
0 |
0 |
| T94 |
0 |
6 |
0 |
0 |
| T106 |
87384 |
1 |
0 |
0 |
| T107 |
82551 |
1 |
0 |
0 |
| T121 |
0 |
3 |
0 |
0 |
| T205 |
87989 |
8 |
0 |
0 |
| T206 |
0 |
8 |
0 |
0 |
| T295 |
202705 |
0 |
0 |
0 |