Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T97,T102,T155	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T232,T233,T204	Yes	T232,T233,T204	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T45,T232,T233	Yes	T45,T232,T233	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T37,T100,T101	Yes	T37,T100,T101	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T100,T101,T224	Yes	T100,T101,T224	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T100,T101,T224	Yes	T100,T101,T224	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T45,T84,T234	Yes	T45,T84,T234	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T44,T45,T38	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T86,T99,T37	Yes	T86,T99,T37	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T44,T45,T38	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T44,T45,T38	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T86,T99,T37	Yes	T86,T99,T37	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T44,T45,T38	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T86,T99,T37	Yes	T86,T99,T37	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T86,T99,T37	Yes	T86,T99,T37	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T86,T37,T100	Yes	T86,T37,T100	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T86,T99,T37	Yes	T86,T99,T37	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T86,*T99,*T37	Yes	T86,T99,T37	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T86,T99,T37	Yes	T86,T99,T37	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T69,T96,T97	Yes	T69,T96,T97	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T96,T97	Yes	T69,T96,T97	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T69,T96,T97	Yes	T69,T96,T97	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T69,T96,T97	Yes	T69,T96,T97	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T69,T96,*T97	Yes	T69,T96,T97	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T98,T102,T155	Yes	T98,T102,T155	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T69,T96,T97	Yes	T69,T96,T97	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T69,T97,T102	Yes	T69,T96,T97	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T98,T102,T155	Yes	T97,T98,T102	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T69,T96,T97	Yes	T69,T97,T98	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T97,T98	Yes	T69,T98,T102	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T69,T97,T98	Yes	T69,T97,T98	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T98,T102,T155	Yes	T97,T98,T102	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T69,T98,T102	Yes	T69,T96,T97	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T98,T102,T155	Yes	T98,T102,T155	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T69,*T97,*T98	Yes	T69,T98,T102	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T69,T96,T97	Yes	T69,T96,T97	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T99,T57,T271	Yes	T99,T57,T271	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T99,T57,T271	Yes	T99,T57,T271	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T99,T57,T271	Yes	T99,T57,T271	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T99,T57,T271	Yes	T99,T57,T271	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T99,T57,T271	Yes	T99,T57,T271	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T99,*T57,*T271	Yes	T99,T57,T271	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T99,T57,T271	Yes	T99,T57,T271	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T44,T45,T38	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T99,T57,T271	Yes	T99,T57,T271	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T99,T57,T271	Yes	T99,T57,T271	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T44,T45,T38	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T99,*T57,*T271	Yes	T99,T57,T271	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T44,T45,T38	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T99,T57,T271	Yes	T99,T57,T271	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T198,T85	Yes	T1,T198,T85	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T198,T412,T37	Yes	T198,T412,T37	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T78,T413,T283	Yes	T78,T413,T283	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T78,T413,T283	Yes	T78,T413,T283	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T78,T413,T283	Yes	T78,T413,T283	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T69,T96,*T97	Yes	T69,T96,T97	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T78,T413,T283	Yes	T78,T413,T283	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T78,T413,T283	Yes	T78,T413,T283	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T96,T98,T102	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T413,T283,T414	Yes	T413,T283,T414	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T96,T98	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T413,T283,T414	Yes	T78,T413,T283	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T98,T102	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T69,T98,*T155	Yes	T69,T96,T97	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T96,T98,T102	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T283,*T415,*T416	Yes	T413,T283,T414	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T78,T413,T283	Yes	T78,T413,T283	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T99,*T37,*T100	Yes	T99,T37,T100	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T37,T100,T101	Yes	T37,T100,T101	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T44,T45,T84	Yes	T44,T45,T84	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T99,*T37,*T100	Yes	T99,T37,T100	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T96,*T98,*T102	Yes	T96,T98,T102	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T11,T220,T222	Yes	T11,T220,T222	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T98,*T102,*T155	Yes	T96,T98,T102	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T386,T78,T124	Yes	T386,T78,T124	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T386,T78,T124	Yes	T386,T78,T124	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T386,T78,T124	Yes	T386,T78,T124	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T386,T78,T124	Yes	T386,T78,T124	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T386,T78,T124	Yes	T386,T78,T124	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T386,T78,T124	Yes	T386,T78,T124	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T386,T78,T124	Yes	T386,T78,T124	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T386,T78,T124	Yes	T386,T78,T124	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T386,T124,T22	Yes	T386,T124,T22	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T386,T124,T314	Yes	T386,T78,T124	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T386,T124,T22	Yes	T386,T124,T22	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T97,T98,T102	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T98,*T155,*T230	Yes	T96,T97,T98	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T386,*T124,*T314	Yes	T386,T124,T314	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T386,T78,T124	Yes	T386,T78,T124	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T7,T34,T8	Yes	T7,T34,T8	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T7,T34,T8	Yes	T7,T34,T8	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T7,T34,T8	Yes	T7,T34,T8	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T7,T34,T8	Yes	T7,T34,T8	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T97,*T98,*T102	Yes	T97,T98,T102	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T7,T34,T8	Yes	T7,T34,T8	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T7,T34,T8	Yes	T7,T34,T8	INPUT
tl_usbdev_i.d_error	Yes	Yes	T98,T102,T155	Yes	T96,T98,T102	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T34,T8	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T34,T8	Yes	T7,T8,T9	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T7,T34,T8	Yes	T7,T8,T9	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T97,T98,T102	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T98,*T155,*T230	Yes	T97,T98,T102	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T96,T97,T98	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T7,*T8,*T9	Yes	T7,T8,T9	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T7,T34,T8	Yes	T7,T34,T8	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T101,*T97,*T98	Yes	T101,T97,T98	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T13,T44,T26	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T13,T6,T44	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T101,*T98,*T155	Yes	T101,T97,T98	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T101,T96,T97	Yes	T101,T96,T97	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T101,T97,T98	Yes	T101,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T101,T96,T97	Yes	T101,T96,T97	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T101,T98,T102	Yes	T101,T98,T102	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T101,T96,T97	Yes	T101,T96,T97	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T101,*T97,T98	Yes	T101,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T101,T96,T97	Yes	T101,T96,T97	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T101,T97,T102	Yes	T101,T96,T97	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T101,T97,T98	Yes	T101,T96,T98	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T101,T96,T97	Yes	T101,T98,T102	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T101,T98,T102	Yes	T101,T98,T102	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T98,T102,T155	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T101,T98,T102	Yes	T101,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T98,T102,T155	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T101,*T98,*T102	Yes	T101,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T101,T96,T97	Yes	T101,T96,T97	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T13,T44,T26	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T78,T311,T649	Yes	T78,T311,T649	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T78,T311,T649	Yes	T78,T311,T649	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T78,T311,T649	Yes	T78,T311,T649	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T78,T311,T649	Yes	T78,T311,T649	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T78,T311,T649	Yes	T78,T311,T649	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T101,*T96,*T97	Yes	T101,T96,T97	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T311,T649,T312	Yes	T311,T649,T312	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T78,T311,T649	Yes	T78,T311,T649	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T78,T311,T649	Yes	T78,T311,T649	INPUT
tl_hmac_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T311,T649,T312	Yes	T311,T649,T312	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T311,T649,T312	Yes	T311,T649,T312	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T78,T311,T649	Yes	T311,T649,T312	INPUT
tl_hmac_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T101,*T97,*T98	Yes	T101,T96,T97	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T78,*T311,*T649	Yes	T311,T649,T312	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T78,T311,T649	Yes	T78,T311,T649	INPUT
tl_kmac_o.d_ready	Yes	Yes	T13,T107,T44	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T107,T78,T449	Yes	T107,T78,T449	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T107,T38,T235	Yes	T107,T38,T235	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T107,T38,T235	Yes	T107,T38,T235	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T107,T78,T449	Yes	T107,T78,T449	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T107,T38,T235	Yes	T107,T38,T235	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T101,*T69,*T96	Yes	T101,T69,T96	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T107,T449,T450	Yes	T107,T449,T450	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T107,T38,T235	Yes	T107,T38,T235	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T107,T38,T235	Yes	T107,T38,T235	INPUT
tl_kmac_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T107,T38,T235	Yes	T107,T38,T235	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T107,T38,T235	Yes	T107,T38,T235	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T107,T38,T235	Yes	T107,T38,T200	INPUT
tl_kmac_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T101,*T69,*T98	Yes	T101,T69,T96	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T97,T98,T155	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T107,*T38,*T235	Yes	T107,T38,T200	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T107,T38,T235	Yes	T107,T38,T235	INPUT
tl_aes_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T100,*T96,*T97	Yes	T100,T96,T97	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T98,T102,T155	Yes	T98,T102,T155	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	INPUT
tl_aes_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	INPUT
tl_aes_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T100,*T96,*T98	Yes	T100,T96,T97	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T280,*T281,*T291	Yes	T280,T281,T291	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T280,T281,T291	Yes	T280,T281,T291	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T101,*T96,*T97	Yes	T101,T96,T97	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T97,T98,T155	Yes	T97,T98,T102	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T153,T154,T150	Yes	T153,T154,T150	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T101,*T98,*T155	Yes	T101,T96,T97	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T155	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T153,*T154,*T150	Yes	T153,T154,T150	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T291,T78,T153	Yes	T291,T78,T153	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T100,*T101,*T96	Yes	T100,T101,T96	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T97,T98,T102	Yes	T96,T97,T98	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T291,T153,T616	Yes	T291,T153,T616	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T100,*T101,*T98	Yes	T100,T101,T97	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T98,T102,T155	Yes	T96,T97,T98	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T291,*T153,*T616	Yes	T291,T153,T616	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T291,T78,T153	Yes	T291,T78,T153	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T291,T78,T153	Yes	T291,T78,T153	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T101,*T96,*T97	Yes	T101,T96,T97	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T291,T153,T150	Yes	T291,T153,T150	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T101,*T97,*T98	Yes	T101,T96,T97	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T291,*T153,*T150	Yes	T291,T153,T150	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T78,T153,T150	Yes	T78,T153,T150	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T78,T153,T150	Yes	T78,T153,T150	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T78,T153,T150	Yes	T78,T153,T150	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T78,T153,T150	Yes	T78,T153,T150	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T78,T153,T150	Yes	T78,T153,T150	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T101,*T97,*T98	Yes	T101,T97,T98	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T98,T102,T155	Yes	T98,T102,T155	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T78,T153,T150	Yes	T78,T153,T150	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T78,T153,T150	Yes	T78,T153,T150	INPUT
tl_edn1_i.d_error	Yes	Yes	T98,T102,T155	Yes	T96,T98,T102	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T153,T150,T313	Yes	T153,T150,T313	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T150,T313,T265	Yes	T78,T153,T150	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T150,T313,T265	Yes	T78,T153,T150	INPUT
tl_edn1_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T96,T98,T155	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T101,*T98,*T155	Yes	T101,T97,T98	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T97,T98,T102	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T153,*T150,*T313	Yes	T153,T150,T313	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T78,T153,T150	Yes	T78,T153,T150	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T13,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T6,T72	Yes	T5,T6,T72	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T96,T102,T155	Yes	T96,T102,T155	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T98,*T102,*T155	Yes	T96,T97,T98	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otbn_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T208,T78,T150	Yes	T208,T78,T150	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T208,T78,T150	Yes	T208,T78,T150	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T208,T78,T150	Yes	T208,T78,T150	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T208,T78,T150	Yes	T208,T78,T150	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T208,T78,T150	Yes	T208,T78,T150	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T37,*T224,*T225	Yes	T37,T224,T225	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T96,T98,T102	Yes	T96,T98,T102	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T208,T78,T150	Yes	T208,T78,T150	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T208,T78,T150	Yes	T208,T78,T150	INPUT
tl_otbn_i.d_error	Yes	Yes	T97,T98,T102	Yes	T96,T97,T98	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T208,T150,T313	Yes	T208,T150,T313	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T208,T150,T313	Yes	T208,T150,T313	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T208,T78,T150	Yes	T208,T150,T313	INPUT
tl_otbn_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T37,*T224,*T225	Yes	T37,T224,T225	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T208,*T78,*T150	Yes	T208,T150,T313	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T208,T78,T150	Yes	T208,T78,T150	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T38,T235,T200	Yes	T38,T235,T200	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T38,T235,T200	Yes	T38,T235,T200	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T38,T235,T200	Yes	T38,T235,T200	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T38,T200,T236	Yes	T38,T200,T236	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T38,T235,T200	Yes	T38,T235,T200	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T101,*T97,*T98	Yes	T101,T97,T98	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T38,T235,T200	Yes	T38,T235,T200	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T38,T235,T200	Yes	T38,T235,T200	INPUT
tl_keymgr_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T38,T200,T236	Yes	T38,T200,T236	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T38,T200,T236	Yes	T38,T200,T236	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T38,T200,T236	Yes	T38,T200,T236	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T97,T98,T155	Yes	T97,T98,T102	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T101,*T98,*T155	Yes	T101,T97,T98	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T97,T98,T155	Yes	T97,T98,T102	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T38,*T200,*T236	Yes	T38,T235,T200	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T38,T235,T200	Yes	T38,T235,T200	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T271,*T69,*T96	Yes	T271,T69,T96	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T97,T98,T155	Yes	T97,T98,T155	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T69,T96,T98	Yes	T69,T96,T97	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T10,T13	Yes	T4,T10,T13	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T10,T13	Yes	T4,T10,T13	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T69,*T96,*T98	Yes	T271,T69,T96	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T96,T98,T102	Yes	T96,T98,T155	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T13,T44,T26	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T78,T201,T146	Yes	T78,T201,T146	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T78,T201,T146	Yes	T78,T201,T146	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T78,T201,T146	Yes	T78,T201,T146	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T78,T201,T146	Yes	T78,T201,T146	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T78,T201,T146	Yes	T78,T201,T146	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T441,*T442,*T96	Yes	T441,T442,T96	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T78,T201,T146	Yes	T78,T201,T146	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T78,T201,T146	Yes	T78,T201,T146	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T204,T300,T301	Yes	T204,T300,T301	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T201,T146,T204	Yes	T78,T201,T146	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T201,T146,T204	Yes	T78,T201,T146	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T96,*T98,*T155	Yes	T441,T442,T96	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T201,*T146,*T204	Yes	T201,T146,T204	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T78,T201,T146	Yes	T78,T201,T146	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T13,T44,T26	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range