Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.34 99.34

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 99.02 99.02
tb.dut.top_earlgrey.u_edn0 99.25 99.25


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 75 96.15
Total Bits 1210 1202 99.34
Total Bits 0->1 605 602 99.50
Total Bits 1->0 605 600 99.17

Ports 78 75 96.15
Port Bits 1210 1202 99.34
Port Bits 0->1 605 602 99.50
Port Bits 1->0 605 600 99.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T13,T44,T26 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T291,T78,T153 Yes T291,T78,T153 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T291,T78,T153 Yes T291,T78,T153 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T96,*T97,*T98 Yes T96,T97,T98 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T101,*T96,*T97 Yes T101,T96,T97 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T96,T97,T98 Yes T96,T97,T98 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T96,T97,T98 Yes T96,T97,T98 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T96,T97,T98 Yes T96,T97,T98 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T291,T153,T150 Yes T291,T153,T150 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T13,T44,T26 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T13,T44,T26 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T96,T97,T98 Yes T96,T97,T98 OUTPUT
tl_o.d_source[5:0] Yes Yes *T101,*T97,*T98 Yes T101,T96,T97 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T96,T97,T98 Yes T96,T97,T98 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T291,*T153,*T150 Yes T291,T153,T150 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T38,T200,T236 Yes T38,T200,T236 INPUT
edn_i[1].edn_req Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
edn_i[2].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T107,T140,T256 Yes T107,T140,T256 INPUT
edn_i[4].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T38,T200,T236 Yes T38,T200,T236 OUTPUT
edn_o[0].edn_fips Yes Yes T150,T272,T273 Yes T150,T313,T140 OUTPUT
edn_o[0].edn_ack Yes Yes T38,T200,T236 Yes T38,T200,T236 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[1].edn_fips No No Yes T176,T177,T178 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T7,T10 Yes T2,T3,T106 OUTPUT
edn_o[2].edn_fips Yes Yes T137,T138,T139 Yes T140,T141,T142 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T107,T256,T22 Yes T107,T140,T256 OUTPUT
edn_o[3].edn_fips No No Yes T140,T256,T22 OUTPUT
edn_o[3].edn_ack Yes Yes T107,T140,T256 Yes T107,T140,T256 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T13,T44,T26 Yes T106,T13,T107 OUTPUT
edn_o[4].edn_fips Yes Yes T138,T619 Yes T178,T620,T138 OUTPUT
edn_o[4].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T272,T273,T618 Yes T140,T272,T256 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T150,T272,T273 Yes T150,T313,T140 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T4,T13,T5 Yes T4,T106,T13 OUTPUT
edn_o[7].edn_fips Yes Yes T150,T272,T273 Yes T150,T265,T140 OUTPUT
edn_o[7].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T13,T44,T26 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T150,T403,T137 Yes T150,T313,T265 INPUT
csrng_cmd_i.genbits_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T291,T151,T272 Yes T291,T151,T272 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T291,T78,T103 Yes T291,T78,T103 INPUT
alert_rx_i[0].ping_n Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_rx_i[0].ping_p Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T78,T103,T104 Yes T78,T103,T104 INPUT
alert_rx_i[1].ping_n Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_rx_i[1].ping_p Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T291,T78,T103 Yes T291,T78,T103 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T78,T103,T104 Yes T78,T103,T104 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T302,T327,T328 Yes T302,T327,T328 OUTPUT
intr_edn_fatal_err_o Yes Yes T302,T319,T320 Yes T302,T319,T320 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 714 707 99.02
Total Bits 0->1 357 354 99.16
Total Bits 1->0 357 353 98.88

Ports 50 48 96.00
Port Bits 714 707 99.02
Port Bits 0->1 357 354 99.16
Port Bits 1->0 357 353 98.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T13,T44,T26 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T13,T44,T26 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T78,T153,T150 Yes T78,T153,T150 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T78,T153,T150 Yes T78,T153,T150 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T78,T153,T150 Yes T78,T153,T150 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T78,T153,T150 Yes T78,T153,T150 INPUT
tl_i.a_mask[3:0] Yes Yes T78,T153,T150 Yes T78,T153,T150 INPUT
tl_i.a_address[6:0] Yes Yes *T97,*T98,*T102 Yes T97,T98,T102 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T78,T153,T150 Yes T78,T153,T150 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T78,*T153,*T150 Yes T78,T153,T150 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T78,*T153,*T150 Yes T78,T153,T150 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T101,*T97,*T98 Yes T101,T97,T98 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T96,T97,T98 Yes T96,T97,T98 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T98,T102,T155 Yes T98,T102,T155 INPUT
tl_i.a_valid Yes Yes T78,T153,T150 Yes T78,T153,T150 INPUT
tl_o.a_ready Yes Yes T78,T153,T150 Yes T78,T153,T150 OUTPUT
tl_o.d_error Yes Yes T98,T102,T155 Yes T96,T98,T102 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T153,T150,T313 Yes T153,T150,T313 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T150,T313,T265 Yes T78,T153,T150 OUTPUT
tl_o.d_data[31:0] Yes Yes T150,T313,T265 Yes T78,T153,T150 OUTPUT
tl_o.d_sink Yes Yes T97,T98,T102 Yes T96,T98,T155 OUTPUT
tl_o.d_source[5:0] Yes Yes *T101,*T98,*T155 Yes T101,T97,T98 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T96,T97,T98 Yes T97,T98,T102 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T153,*T150,*T313 Yes T153,T150,T313 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T78,T153,T150 Yes T78,T153,T150 OUTPUT
edn_i[0].edn_req Yes Yes T150,T313,T140 Yes T150,T313,T140 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T150,T313,T140 Yes T150,T313,T140 OUTPUT
edn_o[0].edn_fips Yes Yes T150,T272,T273 Yes T150,T313,T140 OUTPUT
edn_o[0].edn_ack Yes Yes T150,T313,T140 Yes T150,T313,T140 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T150,T313,T265 Yes T150,T313,T265 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T150,T313,T151 Yes T150,T313,T265 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T150,T313,T265 Yes T150,T313,T265 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T150,T313,T151 Yes T150,T313,T151 INPUT
csrng_cmd_i.genbits_fips No No Yes T150,T403,T617 INPUT
csrng_cmd_i.genbits_valid Yes Yes T150,T313,T265 Yes T150,T313,T265 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T150,T313,T265 Yes T150,T313,T265 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T272,T273,T618 Yes T272,T273,T618 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T78,T103,T104 Yes T78,T103,T104 INPUT
alert_rx_i[0].ping_n Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_rx_i[0].ping_p Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T78,T103,T104 Yes T78,T103,T104 INPUT
alert_rx_i[1].ping_n Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_rx_i[1].ping_p Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T78,T103,T104 Yes T78,T103,T104 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T78,T103,T104 Yes T78,T103,T104 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T302,T327,T328 Yes T302,T327,T328 OUTPUT
intr_edn_fatal_err_o Yes Yes T302,T319,T320 Yes T302,T319,T320 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1208 1199 99.25
Total Bits 0->1 604 601 99.50
Total Bits 1->0 604 598 99.01

Ports 78 74 94.87
Port Bits 1208 1199 99.25
Port Bits 0->1 604 601 99.50
Port Bits 1->0 604 598 99.01

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T13,T44,T26 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T291,T78,T153 Yes T291,T78,T153 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T291,T78,T153 Yes T291,T78,T153 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T96,*T98,*T102 Yes T96,T98,T102 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T101,*T96,*T97 Yes T101,T96,T97 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T96,T97,T98 Yes T96,T97,T98 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T96,T97,T98 Yes T96,T97,T98 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T96,T97,T98 Yes T96,T97,T98 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T291,T153,T150 Yes T291,T153,T150 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T13,T44,T26 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T13,T44,T26 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T96,T97,T98 Yes T96,T97,T98 OUTPUT
tl_o.d_source[5:0] Yes Yes *T101,*T97,*T98 Yes T101,T96,T97 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T96,T97,T98 Yes T96,T97,T98 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T291,*T153,*T150 Yes T291,T153,T150 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T38,T200,T236 Yes T38,T200,T236 INPUT
edn_i[1].edn_req Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
edn_i[2].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T107,T140,T256 Yes T107,T140,T256 INPUT
edn_i[4].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T38,T200,T236 Yes T38,T200,T236 OUTPUT
edn_o[0].edn_fips No No Yes T140,T256,T141 OUTPUT
edn_o[0].edn_ack Yes Yes T38,T200,T236 Yes T38,T200,T236 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[1].edn_fips No No Yes T176,T177,T178 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T7,T10 Yes T2,T3,T106 OUTPUT
edn_o[2].edn_fips Yes Yes T137,T138,T139 Yes T140,T141,T142 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T107,T256,T22 Yes T107,T140,T256 OUTPUT
edn_o[3].edn_fips No No Yes T140,T256,T22 OUTPUT
edn_o[3].edn_ack Yes Yes T107,T140,T256 Yes T107,T140,T256 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T13,T44,T26 Yes T106,T13,T107 OUTPUT
edn_o[4].edn_fips Yes Yes T138,T619 Yes T178,T620,T138 OUTPUT
edn_o[4].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T272,T273,T618 Yes T140,T272,T256 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T150,T272,T273 Yes T150,T313,T140 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T4,T13,T5 Yes T4,T106,T13 OUTPUT
edn_o[7].edn_fips Yes Yes T150,T272,T273 Yes T150,T265,T140 OUTPUT
edn_o[7].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T13,T44,T26 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T150,T403,T137 Yes T150,T313,T265 INPUT
csrng_cmd_i.genbits_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T291,T151,T272 Yes T291,T151,T272 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T291,T78,T103 Yes T291,T78,T103 INPUT
alert_rx_i[0].ping_n Yes Yes T103,T104,T105 Yes T103,T104,T257 INPUT
alert_rx_i[0].ping_p Yes Yes T103,T104,T257 Yes T103,T104,T105 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T78,T103,T104 Yes T78,T103,T104 INPUT
alert_rx_i[1].ping_n Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_rx_i[1].ping_p Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T291,T78,T103 Yes T291,T78,T103 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T78,T103,T104 Yes T78,T103,T104 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T302,T327,T328 Yes T302,T327,T328 OUTPUT
intr_edn_fatal_err_o Yes Yes T302,T319,T320 Yes T302,T319,T320 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%