Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_invert_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T29 T75 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T29 T75 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T29 T75 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T5 T29 T75 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T5 T29 T75 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T29 T75 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T29 T75 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T29 T75 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T29 T75 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T5 T29 T75 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T5 T29 T75 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T5 T29 T75 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T29,T75

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T29,T75
1	1	Covered	T5,T29,T75

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T5,T29,T75
1	-	Covered	T5,T29,T75

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T29,T75

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T29,T75
1	1	Covered	T5,T29,T75

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T29,T75
0	0	1	Covered	T5,T29,T75
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T29,T75
0	0	1	Covered	T5,T29,T75
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	93134	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	240	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	93134	0	0
T5	35865	1742	0	0
T6	24364	0	0	0
T14	38050	0	0	0
T26	31929	0	0	0
T29	25131	677	0	0
T34	22353	0	0	0
T36	19347	0	0	0
T44	59886	0	0	0
T69	0	397	0	0
T72	51087	0	0	0
T75	0	788	0	0
T81	0	643	0	0
T82	0	1801	0	0
T83	0	1877	0	0
T107	20852	0	0	0
T174	0	380	0	0
T175	0	822	0	0
T384	0	379	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	240	0	0
T5	35865	5	0	0
T6	24364	0	0	0
T14	38050	0	0	0
T26	31929	0	0	0
T29	25131	2	0	0
T34	22353	0	0	0
T36	19347	0	0	0
T44	59886	0	0	0
T69	0	1	0	0
T72	51087	0	0	0
T75	0	2	0	0
T81	0	2	0	0
T82	0	5	0	0
T83	0	4	0	0
T107	20852	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        0/1     ==>    assign src_qs_o = src_q;
156        0/1     ==>    assign dst_wd_o = src_q;
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T69,T163,T384
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	93612	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	241	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	93612	0	0
T69	410442	436	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	425	0	0
T175	0	784	0	0
T384	0	415	0	0
T407	0	286	0	0
T417	0	754	0	0
T419	0	300	0	0
T420	0	831	0	0
T421	0	595	0	0
T422	0	352	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	241	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T28 T69 T96 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T28 T69 T163 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T28 T69 T163 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T28 T69 T163 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T28 T69 T163 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T28 T69 T163 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T28 T69 T163 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T28 T69 T163 
135        1/1                txn_bits_q <= '0;
           Tests:       T28 T69 T163 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T28 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T28 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T28 T69 T163 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T28,T69,T96

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T28,T69,T163
1	1	Covered	T28,T69,T163

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T69,T163
1	-	Covered	T28

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T28,T69,T163

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T69,T163
1	1	Covered	T28,T69,T163

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T28,T69,T163
0	0	1	Covered	T28,T69,T163
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T28,T69,T163
0	0	1	Covered	T28,T69,T163
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	93093	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	240	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	93093	0	0
T21	26903	0	0	0
T28	31988	839	0	0
T69	0	404	0	0
T81	25896	0	0	0
T133	22017	0	0	0
T174	0	432	0	0
T175	0	868	0	0
T289	67893	0	0	0
T357	46713	0	0	0
T384	0	482	0	0
T407	0	310	0	0
T417	0	759	0	0
T419	0	294	0	0
T420	0	746	0	0
T421	0	560	0	0
T430	232794	0	0	0
T431	71428	0	0	0
T432	167405	0	0	0
T433	62645	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	240	0	0
T21	26903	0	0	0
T28	31988	2	0	0
T69	0	1	0	0
T81	25896	0	0	0
T133	22017	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T289	67893	0	0	0
T357	46713	0	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T430	232794	0	0	0
T431	71428	0	0	0
T432	167405	0	0	0
T433	62645	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        0/1     ==>    assign src_qs_o = src_q;
156        0/1     ==>    assign dst_wd_o = src_q;
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T434,T163

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T69,T163,T384
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	98461	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	250	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	98461	0	0
T69	410442	444	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	422	0	0
T175	0	780	0	0
T384	0	459	0	0
T407	0	314	0	0
T417	0	721	0	0
T419	0	360	0	0
T420	0	780	0	0
T421	0	636	0	0
T422	0	264	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	250	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        0/1     ==>    assign src_qs_o = src_q;
156        0/1     ==>    assign dst_wd_o = src_q;
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T69,T163,T384
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	84945	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	220	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	84945	0	0
T69	410442	403	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	419	0	0
T175	0	825	0	0
T384	0	378	0	0
T407	0	268	0	0
T417	0	695	0	0
T419	0	292	0	0
T420	0	815	0	0
T421	0	560	0	0
T422	0	328	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	220	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T26 T76 T77 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T26 T76 T77 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T26 T76 T77 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T26 T76 T77 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T26 T76 T77 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T26 T76 T77 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T26 T76 T77 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T26 T76 T77 
135        1/1                txn_bits_q <= '0;
           Tests:       T26 T76 T77 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T26 T76 T77 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T26 T76 T77 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T26 T76 T77 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T26,T76,T77

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T76,T77
1	1	Covered	T26,T76,T77

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T26,T76,T77
1	-	Covered	T26,T76,T77

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T26,T76,T77

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T26,T76,T77
1	1	Covered	T26,T76,T77

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T26,T76,T77
0	0	1	Covered	T26,T76,T77
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T26,T76,T77
0	0	1	Covered	T26,T76,T77
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	113524	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	291	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	113524	0	0
T8	44219	0	0	0
T26	31929	821	0	0
T27	0	833	0	0
T32	15413	0	0	0
T33	15595	0	0	0
T38	37447	0	0	0
T45	61201	0	0	0
T58	20255	0	0	0
T76	0	866	0	0
T77	0	857	0	0
T94	0	1554	0	0
T121	0	835	0	0
T128	55960	0	0	0
T182	24292	0	0	0
T183	24273	0	0	0
T418	0	1670	0	0
T432	0	764	0	0
T435	0	744	0	0
T436	0	1546	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	291	0	0
T8	44219	0	0	0
T26	31929	2	0	0
T27	0	2	0	0
T32	15413	0	0	0
T33	15595	0	0	0
T38	37447	0	0	0
T45	61201	0	0	0
T58	20255	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T94	0	4	0	0
T121	0	2	0	0
T128	55960	0	0	0
T182	24292	0	0	0
T183	24273	0	0	0
T418	0	4	0	0
T432	0	2	0	0
T435	0	2	0	0
T436	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        0/1     ==>    assign src_qs_o = src_q;
156        0/1     ==>    assign dst_wd_o = src_q;
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T69,T163,T384
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	93624	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	239	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	93624	0	0
T69	410442	368	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	409	0	0
T175	0	813	0	0
T384	0	369	0	0
T407	0	325	0	0
T417	0	669	0	0
T419	0	344	0	0
T420	0	869	0	0
T421	0	520	0	0
T422	0	286	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	239	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        0/1     ==>    assign src_qs_o = src_q;
156        0/1     ==>    assign dst_wd_o = src_q;
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T69,T163,T384
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	96009	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	243	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	96009	0	0
T69	410442	447	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	431	0	0
T175	0	838	0	0
T384	0	382	0	0
T407	0	311	0	0
T417	0	717	0	0
T419	0	300	0	0
T420	0	799	0	0
T421	0	674	0	0
T422	0	316	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	243	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T29 T75 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T29 T75 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T29 T75 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T5 T29 T75 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T5 T29 T75 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T29 T75 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T29 T75 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T29 T75 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T29 T75 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T5 T82 T83 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T5 T82 T83 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T5 T29 T75 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T29,T75

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T29,T75
1	1	Covered	T5,T29,T75

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T29,T75

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T29,T75
1	1	Covered	T5,T29,T75

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T29,T75
0	0	1	Covered	T5,T29,T75
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T29,T75
0	0	1	Covered	T5,T29,T75
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	102575	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	263	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	102575	0	0
T5	35865	678	0	0
T6	24364	0	0	0
T14	38050	0	0	0
T26	31929	0	0	0
T29	25131	301	0	0
T34	22353	0	0	0
T36	19347	0	0	0
T44	59886	0	0	0
T69	0	414	0	0
T72	51087	0	0	0
T75	0	291	0	0
T81	0	267	0	0
T82	0	616	0	0
T83	0	717	0	0
T107	20852	0	0	0
T174	0	451	0	0
T175	0	863	0	0
T384	0	475	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	263	0	0
T5	35865	2	0	0
T6	24364	0	0	0
T14	38050	0	0	0
T26	31929	0	0	0
T29	25131	1	0	0
T34	22353	0	0	0
T36	19347	0	0	0
T44	59886	0	0	0
T69	0	1	0	0
T72	51087	0	0	0
T75	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	2	0	0
T107	20852	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T69 T163 T384 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T69 T163 T384 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	94224	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	240	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	94224	0	0
T69	410442	400	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	424	0	0
T175	0	817	0	0
T384	0	386	0	0
T407	0	313	0	0
T417	0	667	0	0
T419	0	266	0	0
T420	0	779	0	0
T421	0	556	0	0
T422	0	269	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	240	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T28 T69 T96 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T28 T69 T163 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T28 T69 T163 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T28 T69 T163 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T28 T69 T163 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T28 T69 T163 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T28 T69 T163 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T28 T69 T163 
135        1/1                txn_bits_q <= '0;
           Tests:       T28 T69 T163 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T28 T69 T384 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T28 T69 T384 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T28 T69 T163 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T28,T69,T163

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T28,T69,T163
1	1	Covered	T28,T69,T163

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T28,T69,T163

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T69,T163
1	1	Covered	T28,T69,T163

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T28,T69,T163
0	0	1	Covered	T28,T69,T163
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T28,T69,T163
0	0	1	Covered	T28,T69,T163
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	99120	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	252	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	99120	0	0
T21	26903	0	0	0
T28	31988	300	0	0
T69	0	386	0	0
T81	25896	0	0	0
T133	22017	0	0	0
T174	0	400	0	0
T175	0	931	0	0
T289	67893	0	0	0
T357	46713	0	0	0
T384	0	409	0	0
T407	0	325	0	0
T417	0	669	0	0
T419	0	320	0	0
T420	0	891	0	0
T421	0	605	0	0
T430	232794	0	0	0
T431	71428	0	0	0
T432	167405	0	0	0
T433	62645	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	252	0	0
T21	26903	0	0	0
T28	31988	1	0	0
T69	0	1	0	0
T81	25896	0	0	0
T133	22017	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T289	67893	0	0	0
T357	46713	0	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T430	232794	0	0	0
T431	71428	0	0	0
T432	167405	0	0	0
T433	62645	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T69 T163 T384 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T69 T163 T384 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	87952	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	227	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	87952	0	0
T69	410442	411	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	417	0	0
T175	0	898	0	0
T384	0	407	0	0
T407	0	301	0	0
T417	0	646	0	0
T419	0	320	0	0
T420	0	853	0	0
T421	0	490	0	0
T422	0	316	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	227	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T69 T163 T384 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T69 T163 T384 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	98419	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	252	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	98419	0	0
T69	410442	419	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	403	0	0
T175	0	828	0	0
T384	0	383	0	0
T407	0	279	0	0
T417	0	753	0	0
T419	0	303	0	0
T420	0	809	0	0
T421	0	597	0	0
T422	0	266	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	252	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T26 T76 T77 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T26 T76 T77 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T26 T76 T77 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T26 T76 T77 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T26 T76 T77 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T26 T76 T77 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T26 T76 T77 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T26 T76 T77 
135        1/1                txn_bits_q <= '0;
           Tests:       T26 T76 T77 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T26 T27 T69 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T26 T27 T69 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T26 T76 T77 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T26,T76,T77

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T76,T77
1	1	Covered	T26,T76,T77

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T26,T76,T77

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T26,T76,T77
1	1	Covered	T26,T76,T77

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T26,T76,T77
0	0	1	Covered	T26,T76,T77
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T26,T76,T77
0	0	1	Covered	T26,T76,T77
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	112518	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	288	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	112518	0	0
T8	44219	0	0	0
T26	31929	281	0	0
T27	0	294	0	0
T32	15413	0	0	0
T33	15595	0	0	0
T38	37447	0	0	0
T45	61201	0	0	0
T58	20255	0	0	0
T76	0	370	0	0
T77	0	481	0	0
T94	0	806	0	0
T121	0	338	0	0
T128	55960	0	0	0
T182	24292	0	0	0
T183	24273	0	0	0
T418	0	681	0	0
T432	0	267	0	0
T435	0	247	0	0
T436	0	680	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	288	0	0
T8	44219	0	0	0
T26	31929	1	0	0
T27	0	1	0	0
T32	15413	0	0	0
T33	15595	0	0	0
T38	37447	0	0	0
T45	61201	0	0	0
T58	20255	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T94	0	2	0	0
T121	0	1	0	0
T128	55960	0	0	0
T182	24292	0	0	0
T183	24273	0	0	0
T418	0	2	0	0
T432	0	1	0	0
T435	0	1	0	0
T436	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T69 T163 T384 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T69 T163 T384 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	107371	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	271	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	107371	0	0
T69	410442	370	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	400	0	0
T175	0	832	0	0
T384	0	456	0	0
T407	0	259	0	0
T417	0	656	0	0
T419	0	326	0	0
T420	0	775	0	0
T421	0	663	0	0
T422	0	354	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	271	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T69 T163 T384 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T69 T163 T384 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T437,T163

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	86881	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	224	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	86881	0	0
T69	410442	471	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	437	0	0
T175	0	820	0	0
T384	0	404	0	0
T407	0	334	0	0
T417	0	622	0	0
T419	0	267	0	0
T420	0	948	0	0
T421	0	540	0	0
T422	0	339	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	224	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T69 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T69 T163 T384 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T69 T163 T384 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T69 T163 T384 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T69 T163 T384 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T69 T163 T384 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T69 T163 T384 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T69 T163 T384 
135        1/1                txn_bits_q <= '0;
           Tests:       T69 T163 T384 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T69 T163 T384 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T69 T163 T384 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T69 T163 T384 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T163,T384
1	1	Covered	T69,T163,T384

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T69,T163,T384
0	0	1	Covered	T69,T163,T384
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	85317	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	219	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	85317	0	0
T69	410442	443	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	395	0	0
T175	0	868	0	0
T384	0	425	0	0
T407	0	336	0	0
T417	0	699	0	0
T419	0	315	0	0
T420	0	780	0	0
T421	0	648	0	0
T422	0	329	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	219	0	0
T69	410442	1	0	0
T127	112592	0	0	0
T162	64775	0	0	0
T174	0	1	0	0
T175	0	2	0	0
T384	0	1	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T422	0	1	0	0
T423	42524	0	0	0
T424	58647	0	0	0
T425	57582	0	0	0
T426	34466	0	0	0
T427	53904	0	0	0
T428	59309	0	0	0
T429	70241	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T88 T122 T385 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T88 T122 T385 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T122 T69 T163 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T88 T122 T385 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T88 T122 T385 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T88 T122 T385 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T88 T122 T385 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T122 T69 T163 
135        1/1                txn_bits_q <= '0;
           Tests:       T122 T69 T163 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T88 T122 T385 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T88 T122 T385 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T88 T122 T385 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T88,T122,T385

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T69,T163
1	1	Covered	T88,T122,T385

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T122,T69,T163

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T88,T122,T385
1	1	Covered	T122,T69,T163

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T88,T122,T385
0	0	1	Covered	T122,T69,T163
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T88,T122,T385
0	0	1	Covered	T122,T69,T163
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	145398904	98679	0	0
DstReqKnown_A	1683357	1460033	0	0
SrcAckBusyChk_A	145398904	251	0	0
SrcBusyKnown_A	145398904	144607538	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	98679	0	0
T69	0	430	0	0
T88	40786	309	0	0
T89	38173	0	0	0
T122	0	246	0	0
T159	44865	0	0	0
T174	0	370	0	0
T175	0	831	0	0
T206	22357	0	0	0
T295	51340	0	0	0
T296	16779	0	0	0
T297	42258	0	0	0
T298	107289	0	0	0
T299	30419	0	0	0
T384	0	409	0	0
T385	0	295	0	0
T407	0	341	0	0
T417	0	778	0	0
T419	0	263	0	0
T438	168540	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683357	1460033	0	0
T1	342	169	0	0
T2	404	231	0	0
T3	325	153	0	0
T4	359	185	0	0
T5	558	386	0	0
T7	385	211	0	0
T10	434	262	0	0
T13	404	232	0	0
T106	344	170	0	0
T107	353	181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	251	0	0
T69	0	1	0	0
T91	64491	0	0	0
T122	37702	1	0	0
T174	0	1	0	0
T175	0	2	0	0
T207	20197	0	0	0
T243	134237	0	0	0
T263	27934	0	0	0
T305	38722	0	0	0
T319	96323	0	0	0
T384	0	1	0	0
T387	41333	0	0	0
T407	0	1	0	0
T417	0	2	0	0
T419	0	1	0	0
T420	0	2	0	0
T421	0	2	0	0
T439	23888	0	0	0
T440	164878	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145398904	144607538	0	0
T1	10888	10504	0	0
T2	16385	16041	0	0
T3	19587	18666	0	0
T4	21123	20381	0	0
T5	35865	35437	0	0
T7	20821	20229	0	0
T10	27421	26834	0	0
T13	22056	21473	0	0
T106	22328	21339	0	0
T107	20852	20097	0	0