af2d1709f9| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.575m | 3.173ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.308m | 2.482ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.691m | 2.414ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.893m | 2.864ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 7.695m | 7.211ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 12.674m | 5.756ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.398h | 49.441ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.862h | 64.077ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 19.231m | 10.399ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.862h | 64.077ms | 5 | 5 | 100.00 |
| chip_csr_rw | 12.674m | 5.756ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 15.120s | 230.946us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.749m | 4.073ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.749m | 4.073ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.749m | 4.073ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 12.162m | 4.110ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 12.162m | 4.110ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 11.970m | 4.551ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 10.068m | 4.565ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 11.412m | 3.780ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 44.292m | 12.574ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 26.217m | 9.440ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 31.449m | 14.369ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 220 | 220 | 100.00 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.949m | 6.286ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.949m | 6.286ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.650m | 3.277ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 8.022m | 5.746ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.230m | 3.286ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 26.220m | 15.941ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 15.938m | 9.900ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 9.646m | 7.470ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 23.462m | 11.647ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.441m | 3.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 20.318m | 8.361ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.982m | 5.575ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.982m | 5.575ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 15.304m | 7.967ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 1.037h | 22.506ms | 2 | 3 | 66.67 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 10.588m | 4.779ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.998m | 5.930ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.331h | 19.227ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.557m | 2.370ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.563m | 6.410ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.482m | 3.132ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 31.470m | 10.319ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.495m | 3.365ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.177m | 5.248ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.579m | 2.790ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.654m | 2.857ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 12.868m | 6.080ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.781m | 5.364ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.322m | 2.353ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.781m | 5.364ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 5.157m | 3.093ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.269m | 2.570ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 7.733m | 3.824ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.439m | 2.881ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.975m | 2.960ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 10.519m | 3.972ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.056m | 2.492ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 7.187m | 2.970ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.481m | 3.104ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 40.653m | 9.876ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.025m | 5.832ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 8.537m | 6.701ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.708m | 2.861ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 5.509m | 3.507ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.364m | 2.463ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.711m | 2.830ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.388m | 2.934ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.359m | 3.407ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 12.246m | 4.698ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 5.289h | 81.566ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.149h | 14.493ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 6.944m | 5.930ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 9.134m | 3.983ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 5.514m | 5.024ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 0 | 3 | 0.00 | ||
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 4.550h | 66.558ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 8.864m | 4.450ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 8.864m | 4.450ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.862h | 64.077ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.209h | 29.748ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.695m | 7.211ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 12.674m | 5.756ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.862h | 64.077ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.209h | 29.748ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.695m | 7.211ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 12.674m | 5.756ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 2.179m | 2.468ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 10.680s | 57.322us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.582m | 9.824ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.352m | 6.542ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.160m | 604.882us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 18.317m | 95.123ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 20.492m | 71.358ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.301m | 1.305ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.141m | 1.351ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.736m | 2.417ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.141m | 1.351ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.765m | 4.285ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 39.429m | 188.709ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.901m | 2.694ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 11.202m | 18.823ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 11.662m | 16.908ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 18.879m | 11.205ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 18.281m | 13.491ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.149h | 14.493ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.243h | 29.514ms | 2 | 3 | 66.67 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.157h | 14.789ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 48.295m | 11.941ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.202h | 15.272ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.126h | 15.095ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.168h | 15.675ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.196h | 15.690ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 53.285m | 11.217ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.292h | 15.305ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.245h | 15.390ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.312h | 15.684ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.034h | 14.882ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.565h | 18.252ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 2.044h | 24.214ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 2.020h | 24.592ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 2.072h | 24.718ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.890h | 24.267ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.489h | 17.688ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.831h | 23.723ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.845h | 24.000ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 2.029h | 23.366ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.804h | 22.516ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 47.576m | 11.654ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.027h | 15.455ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.154h | 14.983ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.086h | 14.992ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.124h | 13.872ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 54.482m | 11.175ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.135h | 14.960ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.089h | 14.625ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 1.121h | 13.856ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.017h | 15.030ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 53.187m | 11.764ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.262h | 15.109ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.219h | 15.304ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.177h | 16.342ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.218h | 14.763ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.232h | 15.163ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.211h | 15.816ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.201h | 14.937ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.401h | 17.349ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.694m | 3.489ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 4.557m | 2.370ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.374m | 3.340ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.724m | 3.048ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 43.136m | 13.174ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.172m | 19.342ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.172m | 19.342ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.431m | 4.310ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 8.025m | 5.832ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.431m | 4.310ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.935m | 10.484ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.935m | 10.484ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.557m | 7.023ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 11.364m | 6.072ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 16.862m | 5.996ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.724m | 3.048ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.896m | 3.676ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.606m | 3.107ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 9.415m | 4.905ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 8.712m | 4.980ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 9.843m | 4.263ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 11.084m | 6.165ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 23.655m | 12.437ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.466m | 4.541ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.904m | 4.781ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.116m | 3.963ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.438m | 4.854ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.223m | 4.436ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.237m | 4.160ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 15.304m | 7.967ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 16.485m | 10.768ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.116m | 3.963ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.438m | 4.854ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 10.588m | 4.779ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.998m | 5.930ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.331h | 19.227ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.557m | 2.370ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.563m | 6.410ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.482m | 3.132ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 31.470m | 10.319ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.495m | 3.365ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.177m | 5.248ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.579m | 2.790ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.490m | 2.338ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 9.587m | 5.400ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 19.844m | 7.572ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.267h | 25.332ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.249m | 2.675ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.933m | 3.269ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 33.221m | 12.037ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.513m | 2.967ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 9.834m | 5.297ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 36.238m | 24.079ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 6.690h | 115.121ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 15.304m | 7.967ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.158m | 4.708ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.158m | 4.251ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.748m | 5.342ms | 97 | 100 | 97.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 21.382m | 6.414ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 29.452m | 7.647ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 9.181m | 3.749ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 12.008m | 6.079ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.814m | 2.417ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 19.495m | 7.566ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 29.636m | 25.227ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.027m | 3.028ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.007m | 3.563ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 12.226m | 5.116ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 29.636m | 25.227ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 29.636m | 25.227ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 58.690m | 21.095ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 58.690m | 21.095ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 9.727m | 5.766ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.172m | 19.342ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.744h | 23.061ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 6.017m | 3.529ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 18.124m | 7.536ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 6.017m | 3.529ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 29.452m | 7.647ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 6.056m | 3.047ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 34.441m | 20.672ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 16.456m | 5.365ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.998m | 5.930ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 11.816m | 3.976ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 10.588m | 4.779ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.757h | 44.827ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 34.441m | 20.672ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.308m | 3.558ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 40.058m | 11.522ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 11.460m | 5.678ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.757h | 44.827ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 11.460m | 5.678ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 11.460m | 5.678ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 11.460m | 5.678ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 11.460m | 5.678ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.748m | 5.342ms | 97 | 100 | 97.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 10.068m | 10.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 15.796m | 5.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 10.762m | 4.991ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 10.762m | 4.991ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.532m | 2.955ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.482m | 3.132ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.896m | 3.676ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 5.992m | 3.037ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 24.076m | 7.105ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 12.964m | 5.120ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 12.246m | 4.790ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 13.846m | 5.335ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 10.101m | 3.925ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 40.058m | 11.522ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 31.470m | 10.319ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 39.776m | 13.093ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 43.136m | 13.174ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.381h | 18.743ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.401m | 2.582ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.741m | 2.617ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.495m | 3.365ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 40.058m | 11.522ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 20.087m | 13.081ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.810m | 3.207ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.329m | 3.128ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.606m | 3.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.912m | 4.856ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 26.220m | 15.941ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 9.646m | 7.470ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 23.462m | 11.647ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.427m | 2.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 20.087m | 13.081ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 20.087m | 13.081ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 20.087m | 13.081ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 32.811m | 11.390ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 11.460m | 5.678ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.757h | 44.827ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.488m | 4.497ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 23.042m | 9.950ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 19.555m | 6.851ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 20.577m | 7.580ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.087m | 13.081ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 40.058m | 11.522ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.026m | 8.889ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 17.418m | 9.167ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 10.068m | 10.731ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 16.485m | 10.768ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.466m | 4.541ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.904m | 4.781ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.116m | 3.963ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.438m | 4.854ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.223m | 4.436ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.237m | 4.160ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 26.220m | 15.941ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 9.646m | 7.470ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 23.462m | 11.647ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 21.879m | 24.299ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 4.154m | 3.683ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.376m | 3.588ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.572m | 2.895ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.248m | 3.801ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 41.049m | 34.754ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 21.879m | 24.299ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.845h | 50.247ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.897h | 49.055ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 17.209m | 10.448ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.843h | 48.916ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 41.049m | 34.754ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.765m | 2.820ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.997m | 2.896ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.116m | 2.027ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 20.087m | 13.081ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 34.441m | 20.672ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.478m | 3.444ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 40.058m | 11.522ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.448m | 5.683ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.661m | 3.070ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 34.441m | 20.672ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.478m | 3.444ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 40.058m | 11.522ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.448m | 5.683ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.661m | 3.070ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 20.087m | 13.081ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.579m | 6.136ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.427m | 2.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.488m | 4.497ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 23.042m | 9.950ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 19.555m | 6.851ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 20.577m | 7.580ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.087m | 13.081ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 10.068m | 10.731ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 10.068m | 10.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.651h | 26.809ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.580m | 8.834ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 33.494m | 25.934ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 9.821m | 7.263ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 12.045m | 7.844ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 10.100m | 5.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 31.777m | 26.734ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 28.762m | 12.949ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 14.935m | 10.484ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 24.899m | 12.254ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 7.986m | 4.512ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.580m | 8.834ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 6.218m | 3.859ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 38.618m | 30.971ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 11.621m | 7.646ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 5.364m | 3.022ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 46.266m | 24.976ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 19.495m | 7.566ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 30.446m | 10.660ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 37.168m | 27.963ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.668m | 3.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.748m | 5.342ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.026m | 8.889ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.026m | 8.889ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 30.446m | 10.660ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 46.266m | 24.976ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 7.986m | 4.512ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.025m | 5.832ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 6.864m | 3.954ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 12.283m | 5.747ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.710m | 4.427ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 30.107m | 13.124ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.905m | 3.306ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.748m | 5.342ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 31.293m | 8.626ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 18.137m | 6.217ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.095m | 4.232ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.925m | 4.933ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.019m | 2.863ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.989m | 3.358ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.149h | 14.493ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 13.882m | 6.992ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.301m | 3.479ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 7.026m | 2.830ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 6.055m | 3.428ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 12.448m | 5.683ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.177m | 5.248ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 15.978m | 8.351ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 13.006m | 7.443ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 17.418m | 9.167ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.748m | 5.342ms | 97 | 100 | 97.00 |
| chip_sw_data_integrity_escalation | 12.982m | 5.575ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 5.373m | 2.546ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 3.631m | 3.029ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 7.505m | 3.329ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 7.766m | 3.310ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 24.609m | 7.659ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.408h | 31.879ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 43.258m | 11.982ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.789m | 2.956ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.912m | 4.856ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.748m | 5.342ms | 97 | 100 | 97.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.682m | 3.654ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 30.107m | 13.124ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 9.834m | 5.617ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 8.727m | 3.832ms | 88 | 90 | 97.78 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 22.670m | 11.245ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 21.382m | 6.414ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 31.293m | 8.626ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 21.699m | 8.351ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 3 | 0.00 | ||
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 32.197m | 19.219ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 25.487m | 13.766ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 6.864m | 3.954ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.987m | 5.245ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 9.077m | 6.262ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 9.646m | 7.470ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 21.879m | 24.299ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2625 | 2644 | 99.28 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.048m | 3.548ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 23.122m | 5.324ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 38.748m | 11.670ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 35.594m | 11.669ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 35.922m | 10.838ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.033h | 41.109ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 1.148h | 34.986ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 49.729m | 32.409ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 2.235h | 26.842ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.156m | 3.935ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 8.569m | 2.718ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 20.126m | 5.016ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 31.837m | 8.371ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 10.764m | 3.849ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 17.192m | 5.704ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.519m | 2.891ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 11.017m | 6.554ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 8.325m | 6.780ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 11.322m | 5.678ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 30.446m | 10.660ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.748m | 5.342ms | 97 | 100 | 97.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 6.641m | 3.841ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 12.162m | 4.110ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.304h | 18.944ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 38.748m | 11.670ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 35.594m | 11.669ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 35.922m | 10.838ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 10.563m | 5.808ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 47 | 51 | 92.16 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.632m | 3.372ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 11.965m | 5.931ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 4.954m | 3.048ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.193h | 17.292ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 16.370m | 5.553ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 13.738m | 5.123ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 7.283m | 4.051ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 10.367m | 6.937ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.511m | 3.676ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 3.640m | 2.428ms | 1 | 3 | 33.33 | ||
| chip_sw_flash_ctrl_write_clear | 6.288m | 3.539ms | 3 | 3 | 100.00 | ||
| TOTAL | 2926 | 2951 | 99.15 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 10 | 90.91 |
| V1 | 18 | 18 | 18 | 100.00 |
| V2 | 285 | 270 | 262 | 91.93 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 21 | 23.33 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.17 | 95.52 | 94.02 | 95.39 | -- | 94.99 | 97.53 | 99.59 |
Job timed out after * minutes has 11 failures:
Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.
0.chip_sw_exit_test_unlocked_bootstrap.54206152074180411536154610322714122409551602441588846690558235128880152959825
Log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
1.chip_sw_exit_test_unlocked_bootstrap.6360055965840345614776184709910633217509205018749018936986576718941525597118
Log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
... and 1 more failures.
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.3092014119764422416269083879580840803613779185102018485805526295369977416779
Log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
1.chip_sw_rv_timer_systick_test.49497895599482264944050955207757075353109357583574399445826714007998759460557
Log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
... and 1 more failures.
Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 3 failures.
0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.7339081519815018357792132557903941684439226094373578055973474546509628785609
Log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.61424433611254381237724081062251646000744616668095387984242251817516658470943
Log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
... and 1 more failures.
Test chip_sw_coremark has 1 failures.
0.chip_sw_coremark.98232630452386535886186858287953738931783263174496112733388651112689782231342
Log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
Job timed out after 300 minutes
Test chip_sw_ast_clk_rst_inputs has 1 failures.
0.chip_sw_ast_clk_rst_inputs.33224737937465958751553940546766649055433278934024532906418913435083731614942
Log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
Job timed out after 90 minutes
UVM_ERROR @ * us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A has 6 failures:
0.chip_sw_pwrmgr_sleep_power_glitch_reset.56200736785808577821114155368165232080752187933658726167665090897316204959453
Line 523, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 2770.997404 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 2770.997404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_sleep_power_glitch_reset.96674356802533454883902701891546503416176790301863641105105038790048109543681
Line 408, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 3021.971140 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 3021.971140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.68918683936333307854190489368697789727621060171680350528896992315859893861648
Line 587, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 30971.384160 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 30971.384160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.68402789931401857898070216408078936908212247169783294265001315101299617063332
Line 475, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 20524.366180 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 20524.366180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
32.chip_sw_all_escalation_resets.57565132434450441124606068936448689833017965784594972039913416523345963880933
Line 414, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2649.194766 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2649.194766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
57.chip_sw_all_escalation_resets.89234918930582698108334244475124919009229984788199394992448444152492642404929
Line 427, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2977.686500 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2977.686500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 2 failures:
1.chip_sw_rv_core_ibex_lockstep_glitch.39075820603233331427623585075349160815817354172060378703060636749509380971762
Line 406, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2427.579024 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2427.579024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_rv_core_ibex_lockstep_glitch.115500029565617830244230787772954435412772540926332284391165548832325808830651
Line 417, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2454.272700 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2454.272700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
39.chip_sw_alert_handler_lpg_sleep_mode_alerts.33144594978837817716234540488887201355692839024067918482842795409656734363922
Line 408, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3719.768864 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3719.768864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
67.chip_sw_alert_handler_lpg_sleep_mode_alerts.64206420333780679135673475653293302607888474210891873464897869707777076313065
Line 532, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4194.848200 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 4194.848200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
0.rom_e2e_shutdown_output.24635030167594819145773685420472791935838066513677808134159163261625674501968
Line 639, in log /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 22712.150664 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 22712.150664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---