a861deb3de| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.854m | 2.910ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.591m | 2.890ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.944m | 3.415ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.232m | 2.864ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 8.610m | 6.714ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 13.988m | 6.501ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.567h | 48.254ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 1.858h | 34.838ms | 2 | 5 | 40.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 21.177m | 12.171ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 1.858h | 34.838ms | 2 | 5 | 40.00 |
| chip_csr_rw | 13.988m | 6.501ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 14.860s | 276.278us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.725m | 4.263ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.725m | 4.263ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.725m | 4.263ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 12.088m | 4.577ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 12.088m | 4.577ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 13.835m | 3.821ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 12.831m | 4.849ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 13.848m | 4.650ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 46.142m | 12.836ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 49.936m | 12.719ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 19.582m | 9.043ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 217 | 220 | 98.64 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 6.690m | 6.505ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 6.690m | 6.505ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.170m | 2.914ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 10.441m | 6.614ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 7.152m | 4.282ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 7.379m | 4.438ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 10.570m | 6.661ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 13.511m | 8.286ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 28.889m | 14.841ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.462m | 3.649ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 24.730m | 8.907ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 13.821m | 5.728ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 13.821m | 5.728ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 19.655m | 7.968ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 1.045h | 20.422ms | 2 | 3 | 66.67 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.254m | 3.660ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.799m | 5.986ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.283h | 18.464ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.033m | 2.801ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 21.238m | 6.655ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.485m | 2.535ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.829m | 11.828ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.285m | 3.173ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.476m | 5.188ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.727m | 2.782ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.787m | 3.599ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 15.531m | 7.607ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.916m | 5.548ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.312m | 3.551ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.916m | 5.548ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.705m | 2.925ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.463m | 3.445ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 6.652m | 2.639ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.460m | 3.290ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 5.007m | 3.330ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.466m | 3.704ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.274m | 2.631ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.566m | 2.863ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.059m | 2.926ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 47.083m | 11.097ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.607m | 5.703ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 6.929m | 5.596ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 5.712m | 2.893ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.892m | 3.479ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.656m | 2.779ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 5.688m | 2.751ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.806m | 3.049ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.059m | 2.724ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 10.250m | 5.521ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 5.733h | 79.099ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.284h | 15.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 4.658m | 5.207ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 10.778m | 4.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 11.874m | 10.192ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.601h | 59.306ms | 1 | 3 | 33.33 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 4.660h | 65.905ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 9.367m | 4.523ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 9.367m | 4.523ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 1.858h | 34.838ms | 2 | 5 | 40.00 |
| chip_same_csr_outstanding | 1.433h | 31.504ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.610m | 6.714ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 13.988m | 6.501ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 1.858h | 34.838ms | 2 | 5 | 40.00 |
| chip_same_csr_outstanding | 1.433h | 31.504ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.610m | 6.714ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 13.988m | 6.501ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.903m | 2.462ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 10.940s | 58.144us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.507m | 9.659ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.567m | 6.708ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.233m | 609.546us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 24.969m | 109.803ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 20.881m | 65.204ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.339m | 1.346ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.145m | 1.371ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.850m | 2.525ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.145m | 1.371ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.986m | 4.027ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 50.111m | 155.037ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.760m | 2.665ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 16.602m | 23.961ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 12.843m | 19.021ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 21.742m | 13.594ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 15.567m | 23.128ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.284h | 15.073ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.249h | 25.049ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.252h | 14.748ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 56.343m | 11.701ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.239h | 15.049ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.278h | 15.549ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.280h | 15.363ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.161h | 15.476ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 56.763m | 11.315ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.214h | 15.958ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.332h | 14.853ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.282h | 15.652ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.159h | 15.348ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.662h | 18.574ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 2.126h | 24.407ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 2.258h | 24.248ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 2.100h | 24.297ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 2.250h | 24.013ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.657h | 18.421ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 2.201h | 23.968ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 2.104h | 24.052ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 2.104h | 23.935ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 2.103h | 22.646ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 50.588m | 10.834ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.154h | 14.077ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.184h | 14.312ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.235h | 14.678ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.097h | 13.536ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 57.162m | 11.748ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.134h | 15.125ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.208h | 15.117ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 1.250h | 14.594ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.194h | 14.286ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 1.038h | 11.289ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.311h | 15.316ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.312h | 15.829ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.317h | 15.323ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.285h | 14.518ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.313h | 14.862ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.279h | 15.647ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.259h | 15.337ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.448h | 17.154ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 6.206m | 3.238ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.033m | 2.801ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.354m | 3.163ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.623m | 2.402ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 43.207m | 12.505ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.911m | 18.637ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.911m | 18.637ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 8.036m | 4.368ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 8.607m | 5.703ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 8.036m | 4.368ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 17.034m | 10.049ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 17.034m | 10.049ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 9.212m | 7.615ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.912m | 6.422ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 16.000m | 6.023ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.623m | 2.402ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.760m | 3.504ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.790m | 3.389ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.473m | 5.529ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 10.081m | 5.619ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 9.454m | 5.139ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.696m | 4.476ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 22.481m | 11.389ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.057m | 4.444ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.008m | 5.288ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.252m | 4.111ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.479m | 4.904ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.403m | 3.744ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.454m | 4.877ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 19.655m | 7.968ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 9.613m | 6.586ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.252m | 4.111ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.479m | 4.904ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.254m | 3.660ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.799m | 5.986ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.283h | 18.464ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.033m | 2.801ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 21.238m | 6.655ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.485m | 2.535ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.829m | 11.828ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.285m | 3.173ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.476m | 5.188ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.727m | 2.782ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.400m | 2.944ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 9.977m | 4.666ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 17.894m | 7.544ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.435h | 25.624ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 5.299m | 3.146ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.912m | 3.558ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 29.899m | 11.589ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.412m | 2.690ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 10.935m | 5.131ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 39.975m | 18.572ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 5.803h | 115.310ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 19.655m | 7.968ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.553m | 4.660ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.321m | 4.190ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.717m | 5.645ms | 99 | 100 | 99.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 33.041m | 8.702ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 35.801m | 8.310ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 9.344m | 3.741ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 13.027m | 7.733ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.580m | 2.851ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 17.346m | 6.218ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 33.665m | 23.402ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.746m | 3.503ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 6.237m | 3.743ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.701m | 4.388ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 33.665m | 23.402ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 33.665m | 23.402ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.038h | 20.846ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.038h | 20.846ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.125m | 5.343ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.911m | 18.637ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.965h | 32.344ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.279m | 3.136ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 23.142m | 7.638ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.279m | 3.136ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 35.801m | 8.310ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.300m | 2.850ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 41.974m | 24.814ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.902m | 5.900ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.799m | 5.986ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 12.007m | 3.465ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 12.254m | 3.660ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.860h | 44.206ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 41.974m | 24.814ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.301m | 3.638ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 43.525m | 11.806ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.734m | 4.023ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.860h | 44.206ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.734m | 4.023ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.734m | 4.023ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.734m | 4.023ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.734m | 4.023ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.717m | 5.645ms | 99 | 100 | 99.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 7.505m | 9.285ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 18.134m | 5.979ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 10.886m | 5.912ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 10.886m | 5.912ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 6.393m | 3.433ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.485m | 2.535ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.760m | 3.504ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.591m | 3.367ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 31.992m | 8.112ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 13.648m | 4.704ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 15.096m | 5.502ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 14.055m | 5.968ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 9.044m | 3.622ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 43.525m | 11.806ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 41.829m | 11.828ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 41.708m | 12.506ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 43.207m | 12.505ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.436h | 18.402ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.784m | 2.597ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.318m | 3.559ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.285m | 3.173ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 43.525m | 11.806ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 20.656m | 11.484ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.718m | 2.622ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.668m | 3.141ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.790m | 3.389ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.818m | 5.283ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 7.379m | 4.438ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 13.511m | 8.286ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 28.889m | 14.841ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.154m | 2.947ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 20.656m | 11.484ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 20.656m | 11.484ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 20.656m | 11.484ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 43.674m | 11.346ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.734m | 4.023ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.860h | 44.206ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.677m | 5.207ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 24.186m | 8.897ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.509m | 8.167ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 19.797m | 8.179ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.656m | 11.484ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 43.525m | 11.806ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 10.992m | 8.981ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 17.598m | 9.421ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 7.505m | 9.285ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 9.613m | 6.586ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.057m | 4.444ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.008m | 5.288ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.252m | 4.111ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.479m | 4.904ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.403m | 3.744ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.454m | 4.877ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 7.379m | 4.438ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 13.511m | 8.286ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 28.889m | 14.841ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 12.944m | 11.787ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 4.253m | 3.144ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 3.647m | 3.632ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.429m | 3.271ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 4.264m | 3.900ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 41.889m | 29.162ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 12.944m | 11.787ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 2.042h | 47.704ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 2.111h | 51.657ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 18.604m | 8.251ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 2.020h | 47.846ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 41.889m | 29.162ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.761m | 2.429ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.158m | 1.892ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.928m | 2.414ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 20.656m | 11.484ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 41.974m | 24.814ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.941m | 3.498ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 43.525m | 11.806ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 10.264m | 5.302ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.117m | 2.739ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 41.974m | 24.814ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.941m | 3.498ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 43.525m | 11.806ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 10.264m | 5.302ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.117m | 2.739ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 20.656m | 11.484ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.783m | 3.899ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.154m | 2.947ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.677m | 5.207ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 24.186m | 8.897ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.509m | 8.167ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 19.797m | 8.179ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.656m | 11.484ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 7.505m | 9.285ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 7.505m | 9.285ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.896h | 28.334ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 11.445m | 9.474ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 33.767m | 21.859ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 8.243m | 7.556ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 12.662m | 10.446ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 12.981m | 8.237ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 36.814m | 23.663ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 29.997m | 17.016ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 17.034m | 10.049ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 23.939m | 13.078ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 13.067m | 4.521ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 11.445m | 9.474ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 7.767m | 4.365ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 25.625m | 15.545ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 10.399m | 6.285ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 4.684m | 3.615ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 50.571m | 22.963ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 17.346m | 6.218ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 27.558m | 9.373ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 46.299m | 28.111ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.992m | 3.169ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.717m | 5.645ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 10.992m | 8.981ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 10.992m | 8.981ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 27.558m | 9.373ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 50.571m | 22.963ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 13.067m | 4.521ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.607m | 5.703ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.273m | 3.849ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 14.642m | 6.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 6.537m | 3.460ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 30.771m | 13.110ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 3.921m | 2.651ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.717m | 5.645ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 34.913m | 8.462ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 21.387m | 5.916ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.141m | 4.173ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.466m | 4.037ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.708m | 3.148ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.476m | 2.979ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.284h | 15.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 15.087m | 7.246ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 11.690m | 4.272ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 8.226m | 3.688ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.912m | 2.580ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 10.264m | 5.302ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.476m | 5.188ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 15.600m | 6.587ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 13.010m | 7.804ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 17.598m | 9.421ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.717m | 5.645ms | 99 | 100 | 99.00 |
| chip_sw_data_integrity_escalation | 13.821m | 5.728ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 5.326m | 2.901ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 3.332m | 2.736ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 7.593m | 4.202ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.425m | 3.952ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 28.892m | 8.219ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.441h | 32.173ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 48.122m | 12.484ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.739m | 2.787ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.818m | 5.283ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.717m | 5.645ms | 99 | 100 | 99.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.179m | 3.472ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 30.771m | 13.110ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 10.954m | 5.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.652m | 3.874ms | 87 | 90 | 96.67 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 24.338m | 11.497ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 33.041m | 8.702ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 34.913m | 8.462ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 25.782m | 8.845ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.587h | 254.541ms | 1 | 3 | 33.33 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 37.022m | 19.138ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 26.954m | 14.089ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.273m | 3.849ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 10.046m | 5.400ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 8.598m | 5.980ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 13.511m | 8.286ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 12.944m | 11.787ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2629 | 2644 | 99.43 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 7.218m | 3.452ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 26.130m | 5.693ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 36.656m | 12.060ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 33.846m | 11.267ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 37.886m | 12.312ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 54.154m | 32.518ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 1.144h | 29.310ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 1.114h | 37.425ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 2.347h | 26.296ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 7.729m | 3.295ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 10.170m | 2.997ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 28.473m | 5.966ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 45.476m | 10.418ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 11.614m | 3.663ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 19.111m | 6.037ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 5.272m | 3.111ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 9.315m | 5.624ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 9.817m | 5.579ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 9.995m | 4.393ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 27.558m | 9.373ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.717m | 5.645ms | 99 | 100 | 99.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 6.790m | 3.412ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 12.088m | 4.577ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.343h | 19.061ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 36.656m | 12.060ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 33.846m | 11.267ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 37.886m | 12.312ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 9.974m | 5.554ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 47 | 51 | 92.16 | |||
| Unmapped tests | chip_sival_flash_info_access | 6.352m | 3.225ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 14.205m | 4.924ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 6.226m | 2.635ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.253h | 16.406ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 18.091m | 5.489ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 17.711m | 4.736ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 7.488m | 3.885ms | 2 | 3 | 66.67 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 10.180m | 6.984ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.252m | 3.150ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.586m | 2.966ms | 1 | 3 | 33.33 | ||
| chip_sw_flash_ctrl_write_clear | 6.937m | 3.595ms | 3 | 3 | 100.00 | ||
| TOTAL | 2926 | 2951 | 99.15 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 9 | 81.82 |
| V1 | 18 | 18 | 17 | 94.44 |
| V2 | 285 | 270 | 263 | 92.28 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 21 | 23.33 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.14 | 95.50 | 93.91 | 95.52 | -- | 94.84 | 97.53 | 99.55 |
Job timed out after * minutes has 12 failures:
Test chip_csr_aliasing has 3 failures.
0.chip_csr_aliasing.31332118182673995030937870978877742541380012902126142159702851910618163105853
Log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
Job timed out after 180 minutes
2.chip_csr_aliasing.16108728956211224243522044312932346911609423034862339275034520159890483980824
Log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
Job timed out after 180 minutes
... and 1 more failures.
Test chip_sw_exit_test_unlocked_bootstrap has 2 failures.
0.chip_sw_exit_test_unlocked_bootstrap.94196738095331586094863544268003645492407860631007754202872253609925491258774
Log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
1.chip_sw_exit_test_unlocked_bootstrap.26111499552335320879678052765103315798159480935103702720951655790093656888895
Log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.67111472138293689444076370350263191056528552349800720035176938906087749746629
Log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
1.chip_sw_rv_timer_systick_test.91108168770253372689019606339984537050522952581201113716799610412100355528499
Log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
... and 1 more failures.
Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 2 failures.
0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.100961195677836140251374792648248279313998582121209067701536207826598052579905
Log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.68225898543203475098089985556702547365060992670049435136186036710164592705899
Log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
Test chip_sw_coremark has 1 failures.
0.chip_sw_coremark.102151379004259162424535795828477580741260437229387512166780373745957197718381
Log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
Job timed out after 300 minutes
... and 1 more tests.
UVM_ERROR @ * us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A has 6 failures:
0.chip_sw_pwrmgr_sleep_power_glitch_reset.91114996625326384290794160523181830689240183339607936877947426169565891994705
Line 427, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 2591.126947 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 2591.126947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_sleep_power_glitch_reset.85676742518820148904456754728392654053818661958297179700701019758868625470268
Line 466, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 2941.575792 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 2941.575792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.9006288371713631771612358671453233204526769067084590010228467910825928304539
Line 501, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 8670.510230 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 8670.510230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.8887644729377146156102312022166760210257891503272771539604874572490920471767
Line 447, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 15545.290076 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 15545.290076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
46.chip_sw_alert_handler_lpg_sleep_mode_alerts.61119098427521032379458346659689116795688977613086189495660651674614879421170
Line 399, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3381.579462 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3381.579462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
68.chip_sw_alert_handler_lpg_sleep_mode_alerts.106854255980411820230174337036211912280046280568444256536515818987375103519680
Line 512, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3827.590688 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3827.590688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 2 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.55266804727794842670734288834652989475635328352716165584062273282366522928747
Line 401, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2805.194400 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2805.194400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_core_ibex_lockstep_glitch.113654147166106021762332623331653552984914423719268547863800404892054415223715
Line 416, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2966.334740 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2966.334740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
0.chip_sw_pwrmgr_lowpower_cancel.42089935760142568424051908734309212466505650640657450782058236553373776701345
Line 388, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
UVM_ERROR @ 3917.972000 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 3917.972000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
92.chip_sw_all_escalation_resets.2426164797945093989018656109600882415042776738964580027681238403472094363346
Line 451, in log /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3407.478360 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3407.478360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---