Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3856114	1			T92	109		T93	59		T94	205
values[2]	768418	1			T92	61		T93	26		T94	3
values[3]	97787	1			T93	2		T94	5		T249	14
values[4]	50693	1			T94	9		T462	1		T443	473
values[5]	34995	1			T94	10		T443	342		T698	91
values[6]	26260	1			T94	8		T443	256		T698	59
values[7]	22225	1			T94	7		T443	152		T698	47
values[8]	19372	1			T94	14		T443	118		T698	35
values[9]	17403	1			T94	6		T443	83		T698	23
values[10]	16274	1			T94	9		T443	59		T698	27
values[11]	15476	1			T94	4		T443	47		T698	23
values[12]	14768	1			T94	7		T443	37		T698	17
values[13]	14164	1			T94	2		T443	50		T698	25
values[14]	13349	1			T94	3		T443	36		T698	39
values[15]	12837	1			T94	2		T443	31		T698	43
values[16]	12535	1			T94	7		T443	22		T698	26
values[17]	12118	1			T94	10		T443	21		T698	22
values[18]	11638	1			T94	7		T443	14		T698	19
values[19]	11331	1			T94	10		T443	15		T698	13
values[20]	10865	1			T94	3		T443	10		T698	25
values[21]	10341	1			T94	3		T443	18		T698	11
values[22]	10085	1			T94	6		T443	18		T698	15
values[23]	9825	1			T94	1		T443	16		T698	8
values[24]	9291	1			T94	4		T443	11		T698	10
values[25]	9035	1			T94	10		T443	8		T698	11
values[26]	8436	1			T94	13		T443	12		T698	17
values[27]	8187	1			T94	12		T443	14		T698	22
values[28]	8297	1			T94	10		T443	12		T698	15
values[29]	7565	1			T94	1		T443	27		T698	30
values[30]	6979	1			T443	28		T698	34		T569	10
values[31]	6147	1			T443	12		T698	29		T569	12
values[32]	6038	1			T443	9		T698	19		T569	11
values[33]	5467	1			T443	15		T698	20		T569	7
values[34]	5109	1			T443	14		T698	16		T569	11
values[35]	4761	1			T443	32		T698	13		T569	14
values[36]	4612	1			T443	42		T698	18		T569	19
values[37]	4206	1			T443	32		T698	12		T569	14
values[38]	3928	1			T443	10		T698	10		T569	8
values[39]	3757	1			T443	8		T698	11		T569	5
values[40]	3668	1			T443	4		T698	18		T569	12
values[41]	3408	1			T443	4		T698	12		T569	10
values[42]	3511	1			T443	7		T698	13		T569	8
values[43]	3276	1			T443	3		T698	12		T571	4
values[44]	3330	1			T443	5		T698	10		T571	4
values[45]	3040	1			T443	6		T698	10		T571	2
values[46]	3090	1			T443	5		T698	22		T571	2
values[47]	3078	1			T443	5		T698	21		T571	1
values[48]	3107	1			T443	6		T698	23		T571	4
values[49]	3074	1			T443	10		T698	17		T571	3
values[50]	2958	1			T443	10		T698	9		T571	1
values[51]	2917	1			T443	11		T698	11		T571	2
values[52]	2818	1			T443	15		T698	29		T571	2
values[53]	2685	1			T443	15		T698	9		T571	2
values[54]	2597	1			T443	6		T698	8		T571	2
values[55]	2692	1			T443	6		T698	14		T571	1
values[56]	2537	1			T443	6		T698	8		T571	1
values[57]	2426	1			T443	9		T698	12		T571	2
values[58]	2401	1			T443	8		T698	6		T571	3
values[59]	2406	1			T443	9		T698	13		T571	3
values[60]	2328	1			T443	3		T698	9		T571	5
values[61]	2559	1			T443	1		T698	11		T571	10
values[62]	3888	1			T443	5		T698	11		T571	13
values[63]	10212	1			T443	21		T698	74		T571	27
values[64]	230397	1			T443	51		T698	282		T571	34

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4900557	1			T92	156		T93	72		T94	454
values[2]	835984	1			T92	42		T93	21		T94	125
values[3]	85164	1			T93	3		T94	1		T97	4
values[4]	15065	1			T249	3		T573	3		T556	1
values[5]	5366	1			T249	2		T462	1		T443	14
values[6]	3239	1			T249	1		T443	16		T575	2
values[7]	2464	1			T443	13		T575	2		T698	6
values[8]	2178	1			T443	11		T575	1		T698	4
values[9]	1885	1			T443	6		T575	1		T698	2
values[10]	1689	1			T443	12		T698	5		T665	2
values[11]	1622	1			T443	28		T698	2		T665	7
values[12]	1600	1			T443	15		T698	2		T665	4
values[13]	1488	1			T443	17		T698	2		T665	6
values[14]	1369	1			T443	16		T698	3		T665	7
values[15]	1213	1			T443	13		T698	3		T665	3
values[16]	1146	1			T443	13		T698	5		T665	7
values[17]	1019	1			T443	15		T698	5		T665	6
values[18]	950	1			T443	11		T698	4		T665	7
values[19]	941	1			T443	5		T698	2		T665	7
values[20]	887	1			T443	2		T698	2		T665	3
values[21]	851	1			T443	2		T698	3		T665	1
values[22]	774	1			T443	3		T698	3		T665	3
values[23]	797	1			T443	3		T698	2		T665	1
values[24]	741	1			T443	4		T698	4		T665	3
values[25]	717	1			T443	2		T698	4		T665	4
values[26]	654	1			T443	3		T698	4		T665	3
values[27]	642	1			T443	7		T698	6		T665	1
values[28]	620	1			T443	6		T698	2		T665	1
values[29]	666	1			T443	5		T698	2		T665	1
values[30]	638	1			T443	10		T698	2		T665	3
values[31]	593	1			T443	6		T698	2		T665	9
values[32]	603	1			T443	12		T698	4		T665	5
values[33]	626	1			T443	9		T698	2		T665	8
values[34]	615	1			T443	14		T698	2		T665	12
values[35]	580	1			T443	14		T698	2		T665	19
values[36]	585	1			T443	20		T698	5		T665	8
values[37]	550	1			T443	13		T698	5		T665	3
values[38]	481	1			T443	12		T698	2		T817	8
values[39]	466	1			T443	18		T698	2		T817	9
values[40]	437	1			T443	5		T698	2		T817	2
values[41]	440	1			T443	1		T698	10		T817	4
values[42]	484	1			T443	1		T698	4		T817	2
values[43]	470	1			T443	1		T698	2		T817	3
values[44]	430	1			T443	4		T698	5		T817	6
values[45]	392	1			T443	2		T698	3		T817	2
values[46]	440	1			T443	1		T698	2		T817	2
values[47]	414	1			T443	1		T698	5		T817	6
values[48]	430	1			T443	2		T698	6		T817	3
values[49]	393	1			T443	3		T698	3		T817	6
values[50]	375	1			T443	1		T698	4		T817	8
values[51]	375	1			T443	2		T698	5		T817	9
values[52]	386	1			T698	3		T817	13		T822	2
values[53]	362	1			T698	4		T817	10		T822	4
values[54]	380	1			T698	7		T817	6		T822	1
values[55]	360	1			T698	4		T817	5		T822	3
values[56]	369	1			T698	6		T817	5		T822	1
values[57]	353	1			T698	3		T817	3		T822	4
values[58]	362	1			T698	2		T817	3		T822	1
values[59]	352	1			T698	9		T817	6		T822	1
values[60]	382	1			T698	7		T817	2		T822	1
values[61]	402	1			T698	5		T817	6		T822	1
values[62]	588	1			T698	6		T817	13		T822	2
values[63]	2255	1			T698	23		T817	30		T822	22
values[64]	28025	1			T698	100		T817	55		T822	150

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	573156	1			T92	1		T93	2		T94	2
values[2]	2776634	1			T92	89		T93	26		T94	204
values[3]	1191011	1			T92	36		T93	96		T94	44
values[4]	141150	1			T93	6		T94	4		T99	1
values[5]	72560	1			T94	5		T467	1		T561	4
values[6]	47635	1			T94	7		T467	1		T561	2
values[7]	34983	1			T94	10		T467	1		T561	2
values[8]	28516	1			T94	10		T467	1		T443	157
values[9]	23808	1			T94	3		T467	2		T443	101
values[10]	21088	1			T94	4		T467	2		T443	66
values[11]	19346	1			T94	9		T467	2		T443	54
values[12]	18365	1			T94	4		T467	3		T443	42
values[13]	17337	1			T94	1		T467	2		T443	26
values[14]	16496	1			T94	1		T467	1		T443	30
values[15]	15054	1			T94	5		T467	3		T443	38
values[16]	14439	1			T94	7		T467	1		T443	39
values[17]	14069	1			T94	17		T443	26		T698	23
values[18]	13743	1			T94	13		T443	27		T698	38
values[19]	13235	1			T94	7		T443	37		T698	44
values[20]	12948	1			T94	26		T443	32		T698	32
values[21]	12706	1			T94	12		T443	30		T698	29
values[22]	12150	1			T94	4		T443	27		T698	32
values[23]	11688	1			T94	5		T443	36		T698	34
values[24]	11366	1			T94	5		T443	28		T698	21
values[25]	10693	1			T94	8		T443	29		T698	15
values[26]	10361	1			T94	3		T443	27		T698	13
values[27]	9583	1			T94	1		T443	37		T698	11
values[28]	9174	1			T94	13		T443	45		T698	5
values[29]	8330	1			T94	4		T443	41		T698	4
values[30]	7695	1			T94	1		T443	24		T698	4
values[31]	6867	1			T443	14		T698	7		T569	15
values[32]	6196	1			T443	7		T698	9		T569	18
values[33]	5814	1			T443	10		T698	18		T569	4
values[34]	5492	1			T443	10		T698	12		T569	8
values[35]	5032	1			T443	14		T698	9		T569	7
values[36]	4859	1			T443	19		T698	18		T569	8
values[37]	4380	1			T443	10		T698	9		T569	5
values[38]	4046	1			T443	5		T698	11		T569	9
values[39]	3933	1			T443	13		T698	13		T569	6
values[40]	3802	1			T443	8		T698	13		T569	7
values[41]	3710	1			T443	8		T698	9		T569	5
values[42]	3593	1			T443	12		T698	5		T569	9
values[43]	3517	1			T443	13		T698	6		T569	9
values[44]	3467	1			T443	8		T698	6		T569	7
values[45]	3327	1			T443	4		T698	7		T569	4
values[46]	3258	1			T443	6		T698	5		T569	7
values[47]	3188	1			T443	14		T698	5		T569	7
values[48]	3278	1			T443	11		T698	9		T569	8
values[49]	3170	1			T443	5		T698	10		T569	10
values[50]	3166	1			T443	2		T698	10		T569	9
values[51]	3107	1			T443	3		T698	19		T569	5
values[52]	3083	1			T443	2		T698	9		T569	4
values[53]	2895	1			T443	4		T698	9		T569	11
values[54]	2912	1			T443	14		T698	7		T569	3
values[55]	2865	1			T443	20		T698	8		T569	2
values[56]	2855	1			T443	7		T698	4		T569	1
values[57]	2749	1			T443	2		T698	16		T571	1
values[58]	2676	1			T443	5		T698	12		T571	1
values[59]	2599	1			T443	3		T698	7		T571	2
values[60]	2622	1			T443	3		T698	7		T571	1
values[61]	2651	1			T443	2		T698	5		T571	1
values[62]	3584	1			T443	4		T698	19		T571	6
values[63]	8928	1			T443	20		T698	104		T571	17
values[64]	222958	1			T443	53		T698	339		T571	59