Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2022270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35487281

1

T1

350

T2

3469

T3

4507

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26300500	1			T1	175		T2	797		T3	1434
values[0x0]	9763055	1			T1	175		T2	2672		T3	3073
values[0x1]	1445996	1			T1	3		T2	109		T3	192

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	722339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36787212

1

T1

353

T2

3578

T3

4699

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17458142	1			T1	177		T2	1789		T3	2350
valid_sources[0x01]	17454951	1			T1	176		T2	1789		T3	2349
valid_sources[0x02]	42252	1			T96	1		T407	20		T896	5
valid_sources[0x03]	41857	1			T95	1		T407	26		T896	2
valid_sources[0x04]	41736	1			T36	1		T95	2		T96	1
valid_sources[0x05]	41631	1			T95	2		T96	1		T223	1
valid_sources[0x06]	42045	1			T36	2		T95	1		T407	25
valid_sources[0x07]	41545	1			T36	1		T96	1		T224	2
valid_sources[0x08]	42022	1			T224	1		T225	1		T407	31
valid_sources[0x09]	41897	1			T36	3		T96	1		T407	21
valid_sources[0x0a]	42614	1			T36	1		T96	1		T223	2
valid_sources[0x0b]	41950	1			T96	3		T224	2		T407	26
valid_sources[0x0c]	40732	1			T96	2		T223	2		T407	20
valid_sources[0x0d]	42453	1			T224	1		T407	16		T896	3
valid_sources[0x0e]	42068	1			T36	1		T224	1		T225	2
valid_sources[0x0f]	41244	1			T224	1		T407	18		T896	6
valid_sources[0x10]	40887	1			T95	1		T225	2		T407	19
valid_sources[0x11]	42344	1			T36	7		T95	1		T224	2
valid_sources[0x12]	42415	1			T36	2		T224	1		T225	2
valid_sources[0x13]	41617	1			T36	1		T407	24		T896	1
valid_sources[0x14]	41711	1			T95	1		T223	1		T225	2
valid_sources[0x15]	41938	1			T95	1		T225	1		T407	35
valid_sources[0x16]	41399	1			T96	1		T223	1		T224	4
valid_sources[0x17]	41616	1			T95	1		T224	3		T225	1
valid_sources[0x18]	41851	1			T36	2		T95	2		T407	16
valid_sources[0x19]	41462	1			T223	1		T225	3		T407	27
valid_sources[0x1a]	41595	1			T223	1		T225	1		T407	22
valid_sources[0x1b]	41649	1			T36	1		T95	4		T224	1
valid_sources[0x1c]	45169	1			T223	1		T224	2		T225	1
valid_sources[0x1d]	40974	1			T95	3		T96	2		T223	2
valid_sources[0x1e]	42337	1			T36	4		T224	3		T407	16
valid_sources[0x1f]	42096	1			T95	2		T223	1		T225	3
valid_sources[0x20]	41492	1			T223	2		T224	1		T225	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25496615

1

T1

175

T2

797

T3

1434

values[0x0]

all_enables

biggest_size

9708577

1

T1

175

T2

2672

T3

3073

values[0x1]

all_enables

biggest_size

282089

1

T36

21

T95

16

T96

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2963794	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

468520

1

T92

23

T93

11

T94

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1162725	1			T92	61		T93	29		T94	137
values[0x0]	1108683	1			T92	49		T93	35		T94	133
values[0x1]	1160906	1			T92	60		T93	23		T94	121

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2294168	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1138146

1

T92

58

T93

25

T94

131

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53219	1			T94	4		T99	19		T422	26
valid_sources[0x01]	54783	1			T92	4		T94	8		T97	1
valid_sources[0x02]	52457	1			T92	20		T94	5		T97	1
valid_sources[0x03]	54062	1			T94	7		T99	15		T399	2
valid_sources[0x04]	53174	1			T94	5		T99	9		T249	2
valid_sources[0x05]	54080	1			T92	1		T93	8		T94	4
valid_sources[0x06]	53947	1			T94	3		T99	6		T399	7
valid_sources[0x07]	53305	1			T92	22		T94	7		T98	1
valid_sources[0x08]	53080	1			T93	3		T94	10		T98	3
valid_sources[0x09]	55436	1			T92	4		T94	6		T99	18
valid_sources[0x0a]	53078	1			T92	8		T93	3		T94	6
valid_sources[0x0b]	54152	1			T93	5		T94	8		T99	14
valid_sources[0x0c]	53230	1			T93	4		T94	9		T97	1
valid_sources[0x0d]	53320	1			T94	7		T97	5		T98	2
valid_sources[0x0e]	54339	1			T94	1		T99	15		T399	9
valid_sources[0x0f]	53358	1			T92	3		T93	1		T94	5
valid_sources[0x10]	54610	1			T92	4		T93	1		T94	6
valid_sources[0x11]	53615	1			T93	2		T94	5		T98	1
valid_sources[0x12]	54169	1			T92	5		T93	2		T94	10
valid_sources[0x13]	53062	1			T93	5		T94	8		T97	1
valid_sources[0x14]	54075	1			T94	4		T97	1		T99	10
valid_sources[0x15]	53391	1			T94	7		T97	1		T98	1
valid_sources[0x16]	54510	1			T92	3		T94	5		T97	3
valid_sources[0x17]	52506	1			T94	2		T98	1		T99	8
valid_sources[0x18]	53139	1			T93	1		T94	4		T97	2
valid_sources[0x19]	53246	1			T93	3		T94	7		T98	4
valid_sources[0x1a]	53182	1			T93	2		T94	8		T99	9
valid_sources[0x1b]	54095	1			T93	3		T94	6		T97	1
valid_sources[0x1c]	55171	1			T93	1		T94	7		T98	1
valid_sources[0x1d]	53298	1			T92	8		T94	7		T97	1
valid_sources[0x1e]	53084	1			T94	6		T97	2		T98	1
valid_sources[0x1f]	53055	1			T92	8		T94	4		T97	1
valid_sources[0x20]	53551	1			T92	25		T94	3		T97	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48836

1

T92

3

T93

2

T94

10

values[0x0]

all_enables

biggest_size

370769

1

T92

17

T93

8

T94

36

values[0x1]

all_enables

biggest_size

48915

1

T92

3

T93

1

T94

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3159710	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

513338

1

T92

29

T93

9

T94

93

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1258157	1			T92	71		T93	40		T94	202
values[0x0]	1156779	1			T92	57		T93	23		T94	200
values[0x1]	1258112	1			T92	70		T93	33		T94	178

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2425142	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1247906

1

T92

66

T93

33

T94

201

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58094	1			T92	1		T94	16		T97	2
valid_sources[0x01]	57583	1			T92	1		T97	3		T99	10
valid_sources[0x02]	56552	1			T92	5		T93	2		T97	1
valid_sources[0x03]	56848	1			T92	4		T94	24		T98	3
valid_sources[0x04]	58671	1			T92	3		T93	2		T94	3
valid_sources[0x05]	57586	1			T92	2		T94	2		T98	1
valid_sources[0x06]	58186	1			T92	2		T93	15		T94	11
valid_sources[0x07]	57293	1			T92	4		T93	6		T94	12
valid_sources[0x08]	57075	1			T92	2		T94	13		T97	1
valid_sources[0x09]	57648	1			T92	7		T94	11		T97	1
valid_sources[0x0a]	56984	1			T92	3		T93	2		T98	2
valid_sources[0x0b]	58413	1			T93	2		T94	9		T98	3
valid_sources[0x0c]	56895	1			T92	6		T93	1		T94	8
valid_sources[0x0d]	57106	1			T92	1		T93	1		T94	43
valid_sources[0x0e]	56974	1			T92	4		T93	3		T94	2
valid_sources[0x0f]	57136	1			T92	1		T93	1		T94	67
valid_sources[0x10]	57695	1			T92	1		T94	6		T97	1
valid_sources[0x11]	58092	1			T92	6		T98	1		T99	8
valid_sources[0x12]	57843	1			T92	2		T94	6		T97	2
valid_sources[0x13]	57062	1			T92	7		T94	15		T99	6
valid_sources[0x14]	57191	1			T92	4		T93	1		T97	1
valid_sources[0x15]	58165	1			T92	12		T93	1		T94	11
valid_sources[0x16]	58376	1			T93	2		T94	7		T97	1
valid_sources[0x17]	57577	1			T92	4		T93	2		T94	1
valid_sources[0x18]	57291	1			T92	2		T94	1		T97	3
valid_sources[0x19]	57482	1			T92	2		T94	7		T98	2
valid_sources[0x1a]	57131	1			T92	1		T93	6		T94	1
valid_sources[0x1b]	57497	1			T92	4		T93	1		T94	12
valid_sources[0x1c]	56813	1			T92	5		T93	1		T98	2
valid_sources[0x1d]	57619	1			T93	6		T94	18		T97	1
valid_sources[0x1e]	56597	1			T92	2		T94	2		T97	2
valid_sources[0x1f]	57190	1			T92	2		T97	1		T99	10
valid_sources[0x20]	56671	1			T92	1		T93	2		T94	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53870

1

T92

3

T93

1

T94

10

values[0x0]

all_enables

biggest_size

405533

1

T92

23

T93

8

T94

80

values[0x1]

all_enables

biggest_size

53935

1

T92

3

T94

3

T97

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2979308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

470582

1

T92

19

T93

14

T94

53

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1168564	1			T92	52		T93	44		T94	162
values[0x0]	1112903	1			T92	36		T93	34		T94	136
values[0x1]	1168423	1			T92	38		T93	52		T94	141

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2307478	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1142412

1

T92

35

T93

42

T94

137

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54141	1			T92	1		T94	5		T97	2
valid_sources[0x01]	53755	1			T92	3		T94	8		T97	1
valid_sources[0x02]	52741	1			T92	2		T94	7		T98	3
valid_sources[0x03]	53768	1			T92	2		T93	1		T94	8
valid_sources[0x04]	54407	1			T92	1		T94	7		T97	1
valid_sources[0x05]	54657	1			T92	2		T93	3		T94	13
valid_sources[0x06]	55722	1			T92	3		T93	5		T94	5
valid_sources[0x07]	54413	1			T92	2		T94	7		T99	16
valid_sources[0x08]	53970	1			T92	1		T93	13		T94	6
valid_sources[0x09]	54282	1			T92	1		T93	8		T94	7
valid_sources[0x0a]	53481	1			T92	1		T94	5		T97	2
valid_sources[0x0b]	54487	1			T92	1		T93	13		T94	7
valid_sources[0x0c]	53788	1			T92	2		T94	8		T97	1
valid_sources[0x0d]	53438	1			T92	1		T94	7		T98	2
valid_sources[0x0e]	53630	1			T92	4		T93	1		T94	6
valid_sources[0x0f]	54197	1			T92	3		T93	6		T94	7
valid_sources[0x10]	53947	1			T92	1		T94	5		T99	6
valid_sources[0x11]	54217	1			T93	12		T94	8		T99	17
valid_sources[0x12]	53956	1			T92	3		T94	6		T99	12
valid_sources[0x13]	53634	1			T94	8		T98	2		T99	16
valid_sources[0x14]	53659	1			T94	8		T98	1		T99	11
valid_sources[0x15]	53056	1			T92	2		T94	7		T98	3
valid_sources[0x16]	54875	1			T94	4		T98	1		T99	7
valid_sources[0x17]	53958	1			T92	5		T94	9		T97	1
valid_sources[0x18]	53586	1			T92	3		T93	7		T94	4
valid_sources[0x19]	53685	1			T92	1		T94	6		T98	1
valid_sources[0x1a]	54127	1			T92	3		T93	5		T94	6
valid_sources[0x1b]	53998	1			T93	1		T94	9		T99	5
valid_sources[0x1c]	53675	1			T92	4		T94	4		T98	2
valid_sources[0x1d]	53980	1			T92	3		T93	7		T94	5
valid_sources[0x1e]	53088	1			T92	4		T94	3		T97	1
valid_sources[0x1f]	53936	1			T92	2		T94	8		T97	1
valid_sources[0x20]	53564	1			T92	3		T94	3		T97	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49125

1

T92

2

T94

8

T97

3

values[0x0]

all_enables

biggest_size

371771

1

T92

15

T93

12

T94

40

values[0x1]

all_enables

biggest_size

49686

1

T92

2

T93

2

T94

5