Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Line Coverage for Module : pinmux
Line No.TotalCoveredPercent
TOTAL1279101679.44
CONT_ASSIGN13311100.00
ALWAYS1624545100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN250100.00
CONT_ASSIGN250100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN253100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN254100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN255100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN258100.00
CONT_ASSIGN258100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN274100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN276100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN277100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN278100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN32000
CONT_ASSIGN32111100.00
CONT_ASSIGN42011100.00
ALWAYS4231515100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN528100.00
CONT_ASSIGN528100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN53911100.00
ALWAYS5523266.67
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN58111100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN61211100.00
CONT_ASSIGN612100.00
CONT_ASSIGN612100.00
CONT_ASSIGN612100.00
CONT_ASSIGN61211100.00
CONT_ASSIGN61211100.00
CONT_ASSIGN612100.00
CONT_ASSIGN61211100.00
CONT_ASSIGN61611100.00

Click here to see the source line report.

Cond Coverage for Module : pinmux
TotalCoveredPercent
Conditions1975156879.39
Logical1975156879.39
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
133-49294.44
49272.46
492-49678.41
496-50175.14
501-52884.95
528-59173.57

Toggle Coverage for Module : pinmux
TotalCoveredPercent
Totals 713 395 55.40
Total Bits 3068 2046 66.69
Total Bits 0->1 1534 1024 66.75
Total Bits 1->0 1534 1022 66.62

Ports 713 395 55.40
Port Bits 3068 2046 66.69
Port Bits 0->1 1534 1024 66.75
Port Bits 1->0 1534 1022 66.62

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T37,T31,T32 Yes T1,T2,T3 INPUT
rst_sys_ni Yes Yes T37,T31,T32 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T37,T31,T32 Yes T1,T2,T3 INPUT
pin_wkup_req_o Yes Yes T4,T14,T69 Yes T4,T25,T14 OUTPUT
usb_wkup_req_o Yes Yes T8,T69,T70 Yes T8,T69,T70 OUTPUT
sleep_en_i Yes Yes T1,T2,T3 Yes T4,T6,T25 INPUT
strap_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
strap_en_override_i Unreachable Unreachable Unreachable INPUT
lc_dft_en_i[3:0] Yes Yes T32,T45,T78 Yes T1,T2,T3 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T37,T32,T45 Yes T1,T2,T3 INPUT
lc_check_byp_en_i[3:0] Yes Yes T31,T32,T57 Yes T31,T32,T57 INPUT
lc_escalate_en_i[3:0] Yes Yes T45,T78,T79 Yes T31,T32,T57 INPUT
pinmux_hw_debug_en_o[3:0] Yes Yes T37,T32,T45 Yes T1,T2,T3 OUTPUT
dft_strap_test_o.straps[1:0] No No Yes T80,T81,T82 OUTPUT
dft_strap_test_o.valid Yes Yes T32,T45,T78 Yes T1,T2,T3 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
lc_jtag_o.tdi Yes Yes T35,T31,T32 Yes T35,T31,T32 OUTPUT
lc_jtag_o.trst_n Yes Yes T31,T32,T57 Yes T35,T31,T32 OUTPUT
lc_jtag_o.tms Yes Yes T35,T31,T32 Yes T35,T31,T32 OUTPUT
lc_jtag_o.tck Yes Yes T35,T31,T32 Yes T35,T31,T32 OUTPUT
lc_jtag_i.tdo_oe Yes Yes T35,T31,T32 Yes T35,T31,T32 INPUT
lc_jtag_i.tdo Yes Yes T35,T31,T32 Yes T35,T31,T32 INPUT
rv_jtag_o.tdi Yes Yes T36,T83,T84 Yes T36,T83,T84 OUTPUT
rv_jtag_o.trst_n Yes Yes T36,T83,T85 Yes T36,T83,T84 OUTPUT
rv_jtag_o.tms Yes Yes T36,T83,T84 Yes T36,T83,T84 OUTPUT
rv_jtag_o.tck Yes Yes T36,T83,T84 Yes T36,T83,T84 OUTPUT
rv_jtag_i.tdo_oe Yes Yes T36,T83,T84 Yes T36,T83,T84 INPUT
rv_jtag_i.tdo Yes Yes T36,T83,T84 Yes T36,T83,T84 INPUT
dft_jtag_o.tdi Yes Yes T83,T80,T86 Yes T83,T80,T86 OUTPUT
dft_jtag_o.trst_n Yes Yes T83,T80,T87 Yes T83,T80,T87 OUTPUT
dft_jtag_o.tms Yes Yes T83,T80,T86 Yes T83,T80,T86 OUTPUT
dft_jtag_o.tck Yes Yes T83,T80,T87 Yes T83,T80,T87 OUTPUT
dft_jtag_i.tdo_oe Yes Yes T83,T88,T89 Yes T83,T88,T89 INPUT
dft_jtag_i.tdo Yes Yes T83,T88,T89 Yes T83,T88,T89 INPUT
usbdev_dppullup_en_i Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
usbdev_dnpullup_en_i Yes Yes T7,T8,T90 Yes T7,T8,T90 INPUT
usb_dppullup_en_o Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
usb_dnpullup_en_o Yes Yes T7,T8,T90 Yes T7,T8,T90 OUTPUT
usbdev_suspend_req_i Yes Yes T8,T69,T70 Yes T8,T69,T70 INPUT
usbdev_wake_ack_i Yes Yes T8,T69,T70 Yes T8,T69,T70 INPUT
usbdev_bus_not_idle_o Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
usbdev_bus_reset_o Yes Yes T8,T91 Yes T8,T91 OUTPUT
usbdev_sense_lost_o Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
usbdev_wake_detect_active_o Yes Yes T8,T69,T70 Yes T8,T69,T70 OUTPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[11:0] Yes Yes *T92,*T93,*T94 Yes T92,T93,T94 INPUT
tl_i.a_address[16:12] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T36,*T84,*T95 Yes T36,T84,T95 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T92,T93,T94 Yes T92,T93,T94 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T36,T95,T96 Yes T36,T95,T96 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T93,T97,T98 Yes T93,T97,T98 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T92,T93,T97 Yes T92,T93,T97 OUTPUT
tl_o.d_source[5:0] Yes Yes *T97,*T98,*T99 Yes T92,T93,T97 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T92,T93,T97 Yes T92,T93,T97 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T72,T100,T101 Yes T72,T100,T101 INPUT
alert_rx_i[0].ping_n Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_rx_i[0].ping_p Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T72,T100,T101 Yes T72,T100,T101 OUTPUT
periph_to_mio_i[74:0] Yes Yes T28,T13,T41 Yes T28,T13,T41 INPUT
periph_to_mio_oe_i[74:0] Yes Yes T28,T42,T43 Yes T4,T14,T28 INPUT
mio_to_periph_o[56:0] Yes Yes T14,T28,T41 Yes T14,T28,T41 OUTPUT
periph_to_dio_i[11:0] Yes Yes *T7,*T8,*T9 Yes T9,T19,T20 INPUT
periph_to_dio_i[13:12] No No No INPUT
periph_to_dio_i[15:14] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
periph_to_dio_oe_i[15:0] Yes Yes T9,T19,T20 Yes T9,T19,T20 INPUT
dio_to_periph_o[15:0] Yes Yes T6,T33,T7 Yes T6,T7,T8 OUTPUT
mio_attr_o[0].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[0].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[0].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[0].keep_en No No No OUTPUT
mio_attr_o[0].schmitt_en No No No OUTPUT
mio_attr_o[0].od_en No No No OUTPUT
mio_attr_o[0].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[0].slew_rate[1:0] No No No OUTPUT
mio_attr_o[0].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[0].drive_strength[3:1] No No No OUTPUT
mio_attr_o[1].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].keep_en No No No OUTPUT
mio_attr_o[1].schmitt_en No No No OUTPUT
mio_attr_o[1].od_en No No No OUTPUT
mio_attr_o[1].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].slew_rate[1:0] No No No OUTPUT
mio_attr_o[1].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].drive_strength[3:1] No No No OUTPUT
mio_attr_o[2].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].pull_en Yes Yes T22,T23,T24 Yes T10,T46,T47 OUTPUT
mio_attr_o[2].pull_select Yes Yes T22,T23,T24 Yes T10,T46,T47 OUTPUT
mio_attr_o[2].keep_en No No No OUTPUT
mio_attr_o[2].schmitt_en No No No OUTPUT
mio_attr_o[2].od_en No No No OUTPUT
mio_attr_o[2].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].slew_rate[1:0] No No No OUTPUT
mio_attr_o[2].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].drive_strength[3:1] No No No OUTPUT
mio_attr_o[3].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].keep_en No No No OUTPUT
mio_attr_o[3].schmitt_en No No No OUTPUT
mio_attr_o[3].od_en No No No OUTPUT
mio_attr_o[3].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].slew_rate[1:0] No No No OUTPUT
mio_attr_o[3].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].drive_strength[3:1] No No No OUTPUT
mio_attr_o[4].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].keep_en No No No OUTPUT
mio_attr_o[4].schmitt_en No No No OUTPUT
mio_attr_o[4].od_en No No No OUTPUT
mio_attr_o[4].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].slew_rate[1:0] No No No OUTPUT
mio_attr_o[4].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].drive_strength[3:1] No No No OUTPUT
mio_attr_o[5].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].keep_en No No No OUTPUT
mio_attr_o[5].schmitt_en No No No OUTPUT
mio_attr_o[5].od_en No No No OUTPUT
mio_attr_o[5].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].slew_rate[1:0] No No No OUTPUT
mio_attr_o[5].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].drive_strength[3:1] No No No OUTPUT
mio_attr_o[6].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].keep_en No No No OUTPUT
mio_attr_o[6].schmitt_en No No No OUTPUT
mio_attr_o[6].od_en No No No OUTPUT
mio_attr_o[6].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].slew_rate[1:0] No No No OUTPUT
mio_attr_o[6].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].drive_strength[3:1] No No No OUTPUT
mio_attr_o[7].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[7].pull_en Yes Yes T22,T23,T24 Yes T15,T50,T51 OUTPUT
mio_attr_o[7].pull_select Yes Yes T22,T23,T24 Yes T15,T50,T51 OUTPUT
mio_attr_o[7].keep_en No No No OUTPUT
mio_attr_o[7].schmitt_en No No No OUTPUT
mio_attr_o[7].od_en No No No OUTPUT
mio_attr_o[7].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[7].slew_rate[1:0] No No No OUTPUT
mio_attr_o[7].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[7].drive_strength[3:1] No No No OUTPUT
mio_attr_o[8].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].keep_en No No No OUTPUT
mio_attr_o[8].schmitt_en No No No OUTPUT
mio_attr_o[8].od_en No No No OUTPUT
mio_attr_o[8].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].slew_rate[1:0] No No No OUTPUT
mio_attr_o[8].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].drive_strength[3:1] No No No OUTPUT
mio_attr_o[9].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[9].pull_en Yes Yes T22,T23,T24 Yes T10,T46,T47 OUTPUT
mio_attr_o[9].pull_select Yes Yes T22,T23,T24 Yes T10,T46,T47 OUTPUT
mio_attr_o[9].keep_en No No No OUTPUT
mio_attr_o[9].schmitt_en No No No OUTPUT
mio_attr_o[9].od_en No No No OUTPUT
mio_attr_o[9].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[9].slew_rate[1:0] No No No OUTPUT
mio_attr_o[9].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[9].drive_strength[3:1] No No No OUTPUT
mio_attr_o[10].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[10].pull_en Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
mio_attr_o[10].pull_select Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
mio_attr_o[10].keep_en No No No OUTPUT
mio_attr_o[10].schmitt_en No No No OUTPUT
mio_attr_o[10].od_en No No No OUTPUT
mio_attr_o[10].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[10].slew_rate[1:0] No No No OUTPUT
mio_attr_o[10].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[10].drive_strength[3:1] No No No OUTPUT
mio_attr_o[11].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].keep_en No No No OUTPUT
mio_attr_o[11].schmitt_en No No No OUTPUT
mio_attr_o[11].od_en No No No OUTPUT
mio_attr_o[11].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].slew_rate[1:0] No No No OUTPUT
mio_attr_o[11].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].drive_strength[3:1] No No No OUTPUT
mio_attr_o[12].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[12].pull_en Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
mio_attr_o[12].pull_select Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
mio_attr_o[12].keep_en No No No OUTPUT
mio_attr_o[12].schmitt_en No No No OUTPUT
mio_attr_o[12].od_en No No No OUTPUT
mio_attr_o[12].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[12].slew_rate[1:0] No No No OUTPUT
mio_attr_o[12].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[12].drive_strength[3:1] No No No OUTPUT
mio_attr_o[13].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[13].pull_en Yes Yes T22,T23,T24 Yes T10,T13,T46 OUTPUT
mio_attr_o[13].pull_select Yes Yes T22,T23,T24 Yes T10,T13,T46 OUTPUT
mio_attr_o[13].keep_en No No No OUTPUT
mio_attr_o[13].schmitt_en No No No OUTPUT
mio_attr_o[13].od_en No No No OUTPUT
mio_attr_o[13].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[13].slew_rate[1:0] No No No OUTPUT
mio_attr_o[13].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[13].drive_strength[3:1] No No No OUTPUT
mio_attr_o[14].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[14].pull_en Yes Yes T22,T23,T24 Yes T10,T13,T46 OUTPUT
mio_attr_o[14].pull_select Yes Yes T22,T23,T24 Yes T10,T13,T46 OUTPUT
mio_attr_o[14].keep_en No No No OUTPUT
mio_attr_o[14].schmitt_en No No No OUTPUT
mio_attr_o[14].od_en No No No OUTPUT
mio_attr_o[14].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[14].slew_rate[1:0] No No No OUTPUT
mio_attr_o[14].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[14].drive_strength[3:1] No No No OUTPUT
mio_attr_o[15].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[15].pull_en Yes Yes T22,T23,T24 Yes T10,T13,T46 OUTPUT
mio_attr_o[15].pull_select Yes Yes T22,T23,T24 Yes T10,T13,T46 OUTPUT
mio_attr_o[15].keep_en No No No OUTPUT
mio_attr_o[15].schmitt_en No No No OUTPUT
mio_attr_o[15].od_en No No No OUTPUT
mio_attr_o[15].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[15].slew_rate[1:0] No No No OUTPUT
mio_attr_o[15].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[15].drive_strength[3:1] No No No OUTPUT
mio_attr_o[16].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].keep_en No No No OUTPUT
mio_attr_o[16].schmitt_en No No No OUTPUT
mio_attr_o[16].od_en No No No OUTPUT
mio_attr_o[16].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].slew_rate[1:0] No No No OUTPUT
mio_attr_o[16].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].drive_strength[3:1] No No No OUTPUT
mio_attr_o[17].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].keep_en No No No OUTPUT
mio_attr_o[17].schmitt_en No No No OUTPUT
mio_attr_o[17].od_en No No No OUTPUT
mio_attr_o[17].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].slew_rate[1:0] No No No OUTPUT
mio_attr_o[17].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].drive_strength[3:1] No No No OUTPUT
mio_attr_o[18].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].keep_en No No No OUTPUT
mio_attr_o[18].schmitt_en No No No OUTPUT
mio_attr_o[18].od_en No No No OUTPUT
mio_attr_o[18].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].slew_rate[1:0] No No No OUTPUT
mio_attr_o[18].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].drive_strength[3:1] No No No OUTPUT
mio_attr_o[19].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].keep_en No No No OUTPUT
mio_attr_o[19].schmitt_en No No No OUTPUT
mio_attr_o[19].od_en No No No OUTPUT
mio_attr_o[19].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].slew_rate[1:0] No No No OUTPUT
mio_attr_o[19].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].drive_strength[3:1] No No No OUTPUT
mio_attr_o[20].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].keep_en No No No OUTPUT
mio_attr_o[20].schmitt_en No No No OUTPUT
mio_attr_o[20].od_en No No No OUTPUT
mio_attr_o[20].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].slew_rate[1:0] No No No OUTPUT
mio_attr_o[20].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].drive_strength[3:1] No No No OUTPUT
mio_attr_o[21].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].keep_en No No No OUTPUT
mio_attr_o[21].schmitt_en No No No OUTPUT
mio_attr_o[21].od_en No No No OUTPUT
mio_attr_o[21].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].slew_rate[1:0] No No No OUTPUT
mio_attr_o[21].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].drive_strength[3:1] No No No OUTPUT
mio_attr_o[22].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[22].pull_en Yes Yes T52,T53,T54 Yes T55,T56,T52 OUTPUT
mio_attr_o[22].pull_select Yes Yes T55,T56,T52 Yes T55,T56,T52 OUTPUT
mio_attr_o[22].keep_en No No No OUTPUT
mio_attr_o[22].schmitt_en No No No OUTPUT
mio_attr_o[22].od_en No No No OUTPUT
mio_attr_o[22].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[22].slew_rate[1:0] No No No OUTPUT
mio_attr_o[22].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[22].drive_strength[3:1] No No No OUTPUT
mio_attr_o[23].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].pull_en Yes Yes T52,T53,T54 Yes T55,T56,T52 OUTPUT
mio_attr_o[23].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].keep_en No No No OUTPUT
mio_attr_o[23].schmitt_en No No No OUTPUT
mio_attr_o[23].od_en No No No OUTPUT
mio_attr_o[23].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].slew_rate[1:0] No No No OUTPUT
mio_attr_o[23].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].drive_strength[3:1] No No No OUTPUT
mio_attr_o[24].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].pull_en Yes Yes T52,T53,T54 Yes T55,T56,T52 OUTPUT
mio_attr_o[24].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].keep_en No No No OUTPUT
mio_attr_o[24].schmitt_en No No No OUTPUT
mio_attr_o[24].od_en No No No OUTPUT
mio_attr_o[24].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].slew_rate[1:0] No No No OUTPUT
mio_attr_o[24].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].drive_strength[3:1] No No No OUTPUT
mio_attr_o[25].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[25].pull_en Yes Yes T6,T25,T37 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].pull_select Yes Yes T6,T25,T37 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].keep_en No No No OUTPUT
mio_attr_o[25].schmitt_en No No No OUTPUT
mio_attr_o[25].od_en No No No OUTPUT
mio_attr_o[25].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[25].slew_rate[1:0] No No No OUTPUT
mio_attr_o[25].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[25].drive_strength[3:1] No No No OUTPUT
mio_attr_o[26].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].keep_en No No No OUTPUT
mio_attr_o[26].schmitt_en No No No OUTPUT
mio_attr_o[26].od_en No No No OUTPUT
mio_attr_o[26].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].slew_rate[1:0] No No No OUTPUT
mio_attr_o[26].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].drive_strength[3:1] No No No OUTPUT
mio_attr_o[27].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].keep_en No No No OUTPUT
mio_attr_o[27].schmitt_en No No No OUTPUT
mio_attr_o[27].od_en No No No OUTPUT
mio_attr_o[27].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].slew_rate[1:0] No No No OUTPUT
mio_attr_o[27].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].drive_strength[3:1] No No No OUTPUT
mio_attr_o[28].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].keep_en No No No OUTPUT
mio_attr_o[28].schmitt_en No No No OUTPUT
mio_attr_o[28].od_en No No No OUTPUT
mio_attr_o[28].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].slew_rate[1:0] No No No OUTPUT
mio_attr_o[28].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].drive_strength[3:1] No No No OUTPUT
mio_attr_o[29].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].keep_en No No No OUTPUT
mio_attr_o[29].schmitt_en No No No OUTPUT
mio_attr_o[29].od_en No No No OUTPUT
mio_attr_o[29].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].slew_rate[1:0] No No No OUTPUT
mio_attr_o[29].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].drive_strength[3:1] No No No OUTPUT
mio_attr_o[30].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].keep_en No No No OUTPUT
mio_attr_o[30].schmitt_en No No No OUTPUT
mio_attr_o[30].od_en No No No OUTPUT
mio_attr_o[30].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].slew_rate[1:0] No No No OUTPUT
mio_attr_o[30].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].drive_strength[3:1] No No No OUTPUT
mio_attr_o[31].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].keep_en No No No OUTPUT
mio_attr_o[31].schmitt_en No No No OUTPUT
mio_attr_o[31].od_en No No No OUTPUT
mio_attr_o[31].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].slew_rate[1:0] No No No OUTPUT
mio_attr_o[31].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].drive_strength[3:1] No No No OUTPUT
mio_attr_o[32].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].keep_en No No No OUTPUT
mio_attr_o[32].schmitt_en No No No OUTPUT
mio_attr_o[32].od_en No No No OUTPUT
mio_attr_o[32].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].slew_rate[1:0] No No No OUTPUT
mio_attr_o[32].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].drive_strength[3:1] No No No OUTPUT
mio_attr_o[33].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].keep_en No No No OUTPUT
mio_attr_o[33].schmitt_en No No No OUTPUT
mio_attr_o[33].od_en No No No OUTPUT
mio_attr_o[33].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].slew_rate[1:0] No No No OUTPUT
mio_attr_o[33].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].drive_strength[3:1] No No No OUTPUT
mio_attr_o[34].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].keep_en No No No OUTPUT
mio_attr_o[34].schmitt_en No No No OUTPUT
mio_attr_o[34].od_en No No No OUTPUT
mio_attr_o[34].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].slew_rate[1:0] No No No OUTPUT
mio_attr_o[34].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].drive_strength[3:1] No No No OUTPUT
mio_attr_o[35].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].keep_en No No No OUTPUT
mio_attr_o[35].schmitt_en No No No OUTPUT
mio_attr_o[35].od_en No No No OUTPUT
mio_attr_o[35].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].slew_rate[1:0] No No No OUTPUT
mio_attr_o[35].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].drive_strength[3:1] No No No OUTPUT
mio_attr_o[36].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].keep_en No No No OUTPUT
mio_attr_o[36].schmitt_en No No No OUTPUT
mio_attr_o[36].od_en No No No OUTPUT
mio_attr_o[36].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].slew_rate[1:0] No No No OUTPUT
mio_attr_o[36].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].drive_strength[3:1] No No No OUTPUT
mio_attr_o[37].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].keep_en No No No OUTPUT
mio_attr_o[37].schmitt_en No No No OUTPUT
mio_attr_o[37].od_en No No No OUTPUT
mio_attr_o[37].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].slew_rate[1:0] No No No OUTPUT
mio_attr_o[37].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].drive_strength[3:1] No No No OUTPUT
mio_attr_o[38].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].keep_en No No No OUTPUT
mio_attr_o[38].schmitt_en Yes Yes T31,T32,T57 Yes T35,T31,T32 OUTPUT
mio_attr_o[38].od_en No No No OUTPUT
mio_attr_o[38].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].slew_rate[1:0] No No No OUTPUT
mio_attr_o[38].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].drive_strength[3:1] No No No OUTPUT
mio_attr_o[39].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].keep_en No No No OUTPUT
mio_attr_o[39].schmitt_en Yes Yes T31,T32,T57 Yes T35,T31,T32 OUTPUT
mio_attr_o[39].od_en No No No OUTPUT
mio_attr_o[39].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].slew_rate[1:0] No No No OUTPUT
mio_attr_o[39].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].drive_strength[3:1] No No No OUTPUT
mio_attr_o[40].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].keep_en No No No OUTPUT
mio_attr_o[40].schmitt_en No No No OUTPUT
mio_attr_o[40].od_en No No No OUTPUT
mio_attr_o[40].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].slew_rate[1:0] No No No OUTPUT
mio_attr_o[40].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].drive_strength[3:1] No No No OUTPUT
mio_attr_o[41].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].keep_en No No No OUTPUT
mio_attr_o[41].schmitt_en No No No OUTPUT
mio_attr_o[41].od_en No No No OUTPUT
mio_attr_o[41].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].slew_rate[1:0] No No No OUTPUT
mio_attr_o[41].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].drive_strength[3:1] No No No OUTPUT
mio_attr_o[42].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].keep_en No No No OUTPUT
mio_attr_o[42].schmitt_en No No No OUTPUT
mio_attr_o[42].od_en No No No OUTPUT
mio_attr_o[42].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].slew_rate[1:0] No No No OUTPUT
mio_attr_o[42].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].drive_strength[3:1] No No No OUTPUT
mio_attr_o[43].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].keep_en No No No OUTPUT
mio_attr_o[43].schmitt_en No No No OUTPUT
mio_attr_o[43].od_en No No No OUTPUT
mio_attr_o[43].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].slew_rate[1:0] No No No OUTPUT
mio_attr_o[43].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].drive_strength[3:1] No No No OUTPUT
mio_attr_o[44].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].keep_en No No No OUTPUT
mio_attr_o[44].schmitt_en No No No OUTPUT
mio_attr_o[44].od_en No No No OUTPUT
mio_attr_o[44].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].slew_rate[1:0] No No No OUTPUT
mio_attr_o[44].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].drive_strength[3:1] No No No OUTPUT
mio_attr_o[45].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].keep_en No No No OUTPUT
mio_attr_o[45].schmitt_en No No No OUTPUT
mio_attr_o[45].od_en No No No OUTPUT
mio_attr_o[45].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].slew_rate[1:0] No No No OUTPUT
mio_attr_o[45].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].drive_strength[3:1] No No No OUTPUT
mio_attr_o[46].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].keep_en No No No OUTPUT
mio_attr_o[46].schmitt_en No No No OUTPUT
mio_attr_o[46].od_en No No No OUTPUT
mio_attr_o[46].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].slew_rate[1:0] No No No OUTPUT
mio_attr_o[46].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].drive_strength[3:1] No No No OUTPUT
mio_out_o[46:0] Yes Yes T4,T28,T41 Yes T4,T6,T28 OUTPUT
mio_oe_o[46:0] Yes Yes T28,T42,T43 Yes T4,T6,T28 OUTPUT
mio_in_i[46:0] Yes Yes T4,T28,T39 Yes T4,T28,T39 INPUT
dio_attr_o[0].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T23,T24,T44 Yes T23,T24,T44 OUTPUT
dio_attr_o[0].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[0].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T37,*T32,*T45 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].drive_strength[3:1] No No No OUTPUT
dio_attr_o[1].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].keep_en No No No OUTPUT
dio_attr_o[1].schmitt_en No No No OUTPUT
dio_attr_o[1].od_en No No No OUTPUT
dio_attr_o[1].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].slew_rate[1:0] No No No OUTPUT
dio_attr_o[1].drive_strength[0] Yes Yes *T37,*T32,*T45 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].drive_strength[3:1] No No No OUTPUT
dio_attr_o[2].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T22,T23,T44 Yes T22,T23,T44 OUTPUT
dio_attr_o[2].pull_en Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[2].pull_select Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[2].keep_en No No No OUTPUT
dio_attr_o[2].schmitt_en No No No OUTPUT
dio_attr_o[2].od_en No No No OUTPUT
dio_attr_o[2].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[2].slew_rate[1:0] No No No OUTPUT
dio_attr_o[2].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[2].drive_strength[3:1] No No No OUTPUT
dio_attr_o[3].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[3].pull_en Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[3].pull_select Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[3].keep_en No No No OUTPUT
dio_attr_o[3].schmitt_en No No No OUTPUT
dio_attr_o[3].od_en No No No OUTPUT
dio_attr_o[3].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[3].slew_rate[1:0] No No No OUTPUT
dio_attr_o[3].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[3].drive_strength[3:1] No No No OUTPUT
dio_attr_o[4].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[4].pull_en Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[4].pull_select Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[4].keep_en No No No OUTPUT
dio_attr_o[4].schmitt_en No No No OUTPUT
dio_attr_o[4].od_en No No No OUTPUT
dio_attr_o[4].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[4].slew_rate[1:0] No No No OUTPUT
dio_attr_o[4].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[4].drive_strength[3:1] No No No OUTPUT
dio_attr_o[5].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[5].pull_en Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[5].pull_select Yes Yes T22,T23,T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[5].keep_en No No No OUTPUT
dio_attr_o[5].schmitt_en No No No OUTPUT
dio_attr_o[5].od_en No No No OUTPUT
dio_attr_o[5].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[5].slew_rate[1:0] No No No OUTPUT
dio_attr_o[5].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[5].drive_strength[3:1] No No No OUTPUT
dio_attr_o[6].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].keep_en No No No OUTPUT
dio_attr_o[6].schmitt_en No No No OUTPUT
dio_attr_o[6].od_en No No No OUTPUT
dio_attr_o[6].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].slew_rate[1:0] No No No OUTPUT
dio_attr_o[6].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].drive_strength[3:1] No No No OUTPUT
dio_attr_o[7].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].keep_en No No No OUTPUT
dio_attr_o[7].schmitt_en No No No OUTPUT
dio_attr_o[7].od_en No No No OUTPUT
dio_attr_o[7].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].slew_rate[1:0] No No No OUTPUT
dio_attr_o[7].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].drive_strength[3:1] No No No OUTPUT
dio_attr_o[8].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].keep_en No No No OUTPUT
dio_attr_o[8].schmitt_en No No No OUTPUT
dio_attr_o[8].od_en No No No OUTPUT
dio_attr_o[8].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].slew_rate[1:0] No No No OUTPUT
dio_attr_o[8].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].drive_strength[3:1] No No No OUTPUT
dio_attr_o[9].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].keep_en No No No OUTPUT
dio_attr_o[9].schmitt_en No No No OUTPUT
dio_attr_o[9].od_en No No No OUTPUT
dio_attr_o[9].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].slew_rate[1:0] No No No OUTPUT
dio_attr_o[9].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].drive_strength[3:1] No No No OUTPUT
dio_attr_o[10].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T22,T23,T24 Yes T18,T48,T49 OUTPUT
dio_attr_o[10].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].keep_en No No No OUTPUT
dio_attr_o[10].schmitt_en No No No OUTPUT
dio_attr_o[10].od_en No No No OUTPUT
dio_attr_o[10].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].slew_rate[1:0] No No No OUTPUT
dio_attr_o[10].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].drive_strength[3:1] No No No OUTPUT
dio_attr_o[11].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T22,T23,T24 Yes T18,T48,T49 OUTPUT
dio_attr_o[11].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].keep_en No No No OUTPUT
dio_attr_o[11].schmitt_en No No No OUTPUT
dio_attr_o[11].od_en No No No OUTPUT
dio_attr_o[11].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].slew_rate[1:0] No No No OUTPUT
dio_attr_o[11].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].drive_strength[3:1] No No No OUTPUT
dio_attr_o[12].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[12].virt_od_en No No No OUTPUT
dio_attr_o[12].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[12].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[12].keep_en No No No OUTPUT
dio_attr_o[12].schmitt_en No No No OUTPUT
dio_attr_o[12].od_en No No No OUTPUT
dio_attr_o[12].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[12].slew_rate[1:0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:0] No No No OUTPUT
dio_attr_o[13].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[13].virt_od_en No No No OUTPUT
dio_attr_o[13].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[13].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[13].keep_en No No No OUTPUT
dio_attr_o[13].schmitt_en No No No OUTPUT
dio_attr_o[13].od_en No No No OUTPUT
dio_attr_o[13].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[13].slew_rate[1:0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:0] No No No OUTPUT
dio_attr_o[14].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[14].pull_en Yes Yes T22,T23,T24 Yes T10,T46,T47 OUTPUT
dio_attr_o[14].pull_select Yes Yes T22,T23,T24 Yes T10,T46,T47 OUTPUT
dio_attr_o[14].keep_en No No No OUTPUT
dio_attr_o[14].schmitt_en No No No OUTPUT
dio_attr_o[14].od_en No No No OUTPUT
dio_attr_o[14].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[14].slew_rate[1:0] No No No OUTPUT
dio_attr_o[14].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[14].drive_strength[3:1] No No No OUTPUT
dio_attr_o[15].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[15].pull_en Yes Yes T22,T23,T24 Yes T10,T46,T47 OUTPUT
dio_attr_o[15].pull_select Yes Yes T22,T23,T24 Yes T10,T46,T47 OUTPUT
dio_attr_o[15].keep_en No No No OUTPUT
dio_attr_o[15].schmitt_en No No No OUTPUT
dio_attr_o[15].od_en No No No OUTPUT
dio_attr_o[15].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[15].slew_rate[1:0] No No No OUTPUT
dio_attr_o[15].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[15].drive_strength[3:1] No No No OUTPUT
dio_out_o[11:0] Yes Yes *T6,*T7,*T8 Yes T9,T19,T20 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
dio_oe_o[15:0] Yes Yes T9,T19,T20 Yes T9,T19,T20 OUTPUT
dio_in_i[15:0] Yes Yes T6,T33,T7 Yes T6,T7,T8 INPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : pinmux
Line No.TotalCoveredPercent
Branches 778 571 73.39
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 1 25.00
TERNARY 496 4 1 25.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 1 25.00
TERNARY 496 4 1 25.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 2 50.00
TERNARY 496 4 2 50.00
TERNARY 479 2 2 100.00
TERNARY 483 2 2 100.00
TERNARY 492 4 3 75.00
TERNARY 496 4 3 75.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 2 50.00
TERNARY 532 4 2 50.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 2 50.00
TERNARY 532 4 2 50.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 2 50.00
TERNARY 532 4 2 50.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 2 50.00
TERNARY 532 4 2 50.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 2 50.00
TERNARY 532 4 2 50.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 3 75.00
TERNARY 532 4 3 75.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 3 75.00
TERNARY 532 4 3 75.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 3 75.00
TERNARY 532 4 3 75.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 3 75.00
TERNARY 532 4 3 75.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 3 75.00
TERNARY 532 4 3 75.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 3 75.00
TERNARY 532 4 3 75.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 2 50.00
TERNARY 532 4 2 50.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 1 25.00
TERNARY 532 4 1 25.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 1 25.00
TERNARY 532 4 1 25.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 2 50.00
TERNARY 532 4 2 50.00
TERNARY 515 2 2 100.00
TERNARY 519 2 2 100.00
TERNARY 528 4 1 25.00
TERNARY 532 4 1 25.00
TERNARY 591 2 2 100.00
TERNARY 591 2 1 50.00
TERNARY 591 2 1 50.00
TERNARY 591 2 1 50.00
TERNARY 591 2 2 100.00
TERNARY 591 2 1 50.00
TERNARY 591 2 1 50.00
TERNARY 591 2 1 50.00
IF 162 2 2 100.00
IF 423 2 2 100.00
IF 553 2 1 50.00


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T68,T75
0 1 - Covered T4,T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T68,T75
0 1 - Covered T4,T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T68,T21
0 1 - Covered T4,T68,T75
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T68,T21
0 1 - Covered T4,T68,T75
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T68,T75
0 1 - Covered T6,T38,T68
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T68,T75
0 1 - Covered T6,T38,T68
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T68,T21
0 1 - Covered T68,T75
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T68,T21
0 1 - Covered T68,T75
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T68,T75
0 1 - Covered T4,T6,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T68,T75
0 1 - Covered T4,T6,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T68,T75
0 1 - Covered T4,T68,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T68,T75
0 1 - Covered T4,T68,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T38
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T68,T21
0 1 - Covered T38,T68,T75
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T68,T21
0 1 - Covered T38,T68,T75
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T14
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T14
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T38,T68
0 1 - Covered T4,T68,T75
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T38,T68
0 1 - Covered T4,T68,T75
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T21
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T21
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T38,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T38,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Covered T38,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Covered T38,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T38
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T38
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Covered T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Covered T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T21
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T21
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T38,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T38,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Covered T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Covered T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T6,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T6,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T6,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


479 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


483 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


492 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T38
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


496 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T38
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T38,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T38,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T6,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T6,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T14,T38
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T14,T38
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T76,T77
0 1 - Covered T14,T38,T76
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T76,T77
0 1 - Covered T14,T38,T76
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T14,T38
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T14,T38
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T38,T76
0 1 - Covered T14,T76,T77
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T38,T76
0 1 - Covered T14,T76,T77
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T14,T38
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T14,T38
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T76,T21
0 1 - Covered T14,T76,T77
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T76,T21
0 1 - Covered T14,T76,T77
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T14,T38
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T14,T38
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T76,T21
0 1 - Covered T6,T14,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T76,T21
0 1 - Covered T6,T14,T38
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T38
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T38,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T38,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


515 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


519 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3


528 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


532 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


591 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T14,T76,T77
0 Covered T1,T2,T3


591 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


591 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


591 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


591 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T27
0 Covered T1,T2,T3


591 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


591 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


591 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


162 if (!rst_ni) begin -1- 163 dio_pad_attr_q <= '0; ==> 164 mio_pad_attr_q <= '0; 165 end else begin 166 // dedicated pads 167 for (int kk = 0; kk < NDioPads; kk++) begin ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


423 if (!rst_ni) begin -1- 424 sleep_en_q <= 1'b0; ==> 425 mio_out_retreg_q <= '0; 426 mio_oe_retreg_q <= '0; 427 dio_out_retreg_q <= '0; 428 dio_oe_retreg_q <= '0; 429 end else begin 430 sleep_en_q <= sleep_en_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


553 if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin -1- 554 dio_wkup_no_scan[k] = 1'b0; ==> 555 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T6,T15,T14


Assert Coverage for Module : pinmux
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 25 25 100.00 23 92.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 25 25 100.00 23 92.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 122580651 121931168 0 0
AonWkupReqKnownO_A 1484800 1291895 0 0
DftJtagTckKnown_A 122580651 121931168 0 0
DftJtagTmsKnown_A 122580651 121931168 0 0
DftJtagTrstKnown_A 122580651 121931168 0 0
DftStrapsKnown_A 122580651 121931168 0 0
DioKnownO_A 122580651 121931168 0 0
DioOeKnownO_A 122580651 121931168 0 0
FpvSecCmBusIntegrity_A 122580651 0 0 0
FpvSecCmRegWeOnehotCheck_A 122580651 6 0 0
LcJtagTckKnown_A 122580651 121931168 0 0
LcJtagTmsKnown_A 122580651 121931168 0 0
LcJtagTrstKnown_A 122580651 121931168 0 0
MioKnownO_A 122580651 121931168 0 0
MioOeKnownO_A 122580651 121931168 0 0
PinmuxWkupStable_A 1484800 4340 0 0
PwrMgrStrapSampleOnce0_A 122580651 1672 0 0
PwrMgrStrapSampleOnce1_A 122580651 0 0 969
RvJtagTckKnown_A 122580651 121931168 0 0
RvJtagTmsKnown_A 122580651 121931168 0 0
RvJtagTrstKnown_A 122580651 121931168 0 0
TlAReadyKnownO_A 122580651 121931168 0 0
TlDValidKnownO_A 122580651 121931168 0 0
UsbWakeDetectActiveKnownO_A 1484800 1291895 0 0
UsbWkupReqKnownO_A 1484800 1291895 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

AonWkupReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1484800 1291895 0 0
T1 343 171 0 0
T2 354 182 0 0
T3 481 309 0 0
T4 444 272 0 0
T5 408 235 0 0
T6 439 267 0 0
T15 436 262 0 0
T33 369 196 0 0
T104 387 216 0 0
T105 385 214 0 0

DftJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

DftJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

DftJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

DftStrapsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

DioKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

DioOeKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

FpvSecCmBusIntegrity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 6 0 0
T19 145483 0 0 0
T100 35716 1 0 0
T101 33240 0 0 0
T106 0 1 0 0
T107 0 1 0 0
T108 0 1 0 0
T109 0 1 0 0
T110 0 1 0 0
T111 67663 0 0 0
T112 62707 0 0 0
T113 81528 0 0 0
T114 20291 0 0 0
T115 206599 0 0 0
T116 66002 0 0 0
T117 23720 0 0 0

LcJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

LcJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

LcJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

MioKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

MioOeKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

PinmuxWkupStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1484800 4340 0 0
T4 444 22 0 0
T5 408 0 0 0
T6 439 0 0 0
T10 385 0 0 0
T14 0 73 0 0
T15 436 0 0 0
T25 562 21 0 0
T26 0 21 0 0
T33 369 0 0 0
T35 336 0 0 0
T68 0 89 0 0
T69 0 23 0 0
T70 0 727 0 0
T71 0 555 0 0
T76 0 76 0 0
T104 387 0 0 0
T105 385 0 0 0
T118 0 23 0 0

PwrMgrStrapSampleOnce0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 1672 0 0
T1 10949 1 0 0
T2 16423 1 0 0
T3 20788 1 0 0
T4 24012 1 0 0
T5 24112 1 0 0
T6 27742 1 0 0
T15 29610 1 0 0
T33 23438 1 0 0
T104 19888 1 0 0
T105 18382 1 0 0

PwrMgrStrapSampleOnce1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 0 0 969

RvJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

RvJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

RvJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122580651 121931168 0 0
T1 10949 10512 0 0
T2 16423 15872 0 0
T3 20788 20459 0 0
T4 24012 23491 0 0
T5 24112 23590 0 0
T6 27742 27125 0 0
T15 29610 28893 0 0
T33 23438 22714 0 0
T104 19888 19425 0 0
T105 18382 17958 0 0

UsbWakeDetectActiveKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1484800 1291895 0 0
T1 343 171 0 0
T2 354 182 0 0
T3 481 309 0 0
T4 444 272 0 0
T5 408 235 0 0
T6 439 267 0 0
T15 436 262 0 0
T33 369 196 0 0
T104 387 216 0 0
T105 385 214 0 0

UsbWkupReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1484800 1291895 0 0
T1 343 171 0 0
T2 354 182 0 0
T3 481 309 0 0
T4 444 272 0 0
T5 408 235 0 0
T6 439 267 0 0
T15 436 262 0 0
T33 369 196 0 0
T104 387 216 0 0
T105 385 214 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%