Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T4 T14 T69
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T14,T69 |
| 1 | 0 | Covered | T4,T14,T69 |
| 1 | 1 | Covered | T4,T14,T69 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T14,T69 |
| 1 | 0 | Covered | T4,T14,T69 |
| 1 | 1 | Covered | T4,T14,T69 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
12227 |
0 |
0 |
| T4 |
24456 |
2 |
0 |
0 |
| T5 |
24520 |
0 |
0 |
0 |
| T6 |
28181 |
0 |
0 |
0 |
| T7 |
378 |
0 |
0 |
0 |
| T10 |
23264 |
0 |
0 |
0 |
| T14 |
448 |
7 |
0 |
0 |
| T15 |
30046 |
0 |
0 |
0 |
| T25 |
28247 |
0 |
0 |
0 |
| T29 |
690 |
0 |
0 |
0 |
| T31 |
434 |
0 |
0 |
0 |
| T32 |
509 |
0 |
0 |
0 |
| T33 |
23807 |
0 |
0 |
0 |
| T35 |
9686 |
0 |
0 |
0 |
| T37 |
642 |
0 |
0 |
0 |
| T68 |
0 |
5 |
0 |
0 |
| T69 |
0 |
2 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T75 |
0 |
8 |
0 |
0 |
| T76 |
0 |
7 |
0 |
0 |
| T77 |
0 |
4 |
0 |
0 |
| T104 |
20275 |
0 |
0 |
0 |
| T105 |
18767 |
0 |
0 |
0 |
| T118 |
0 |
2 |
0 |
0 |
| T122 |
0 |
4 |
0 |
0 |
| T130 |
696 |
0 |
0 |
0 |
| T174 |
50677 |
3 |
0 |
0 |
| T180 |
516 |
0 |
0 |
0 |
| T235 |
537 |
0 |
0 |
0 |
| T388 |
0 |
3 |
0 |
0 |
| T389 |
0 |
6 |
0 |
0 |
| T411 |
0 |
1 |
0 |
0 |
| T424 |
0 |
2 |
0 |
0 |
| T425 |
0 |
6 |
0 |
0 |
| T426 |
0 |
1 |
0 |
0 |
| T427 |
0 |
2 |
0 |
0 |
| T428 |
0 |
1 |
0 |
0 |
| T429 |
0 |
2 |
0 |
0 |
| T441 |
450 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
12237 |
0 |
0 |
| T4 |
48468 |
3 |
0 |
0 |
| T5 |
48632 |
0 |
0 |
0 |
| T6 |
55923 |
0 |
0 |
0 |
| T10 |
46143 |
0 |
0 |
0 |
| T14 |
0 |
7 |
0 |
0 |
| T15 |
59656 |
0 |
0 |
0 |
| T25 |
55932 |
0 |
0 |
0 |
| T27 |
487 |
0 |
0 |
0 |
| T33 |
47245 |
0 |
0 |
0 |
| T35 |
19036 |
0 |
0 |
0 |
| T68 |
0 |
6 |
0 |
0 |
| T69 |
0 |
2 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T75 |
0 |
2 |
0 |
0 |
| T76 |
0 |
7 |
0 |
0 |
| T77 |
0 |
4 |
0 |
0 |
| T104 |
40163 |
0 |
0 |
0 |
| T105 |
37149 |
0 |
0 |
0 |
| T118 |
0 |
2 |
0 |
0 |
| T122 |
0 |
4 |
0 |
0 |
| T174 |
154185 |
3 |
0 |
0 |
| T388 |
208539 |
3 |
0 |
0 |
| T389 |
243720 |
6 |
0 |
0 |
| T411 |
141441 |
1 |
0 |
0 |
| T424 |
0 |
2 |
0 |
0 |
| T425 |
261273 |
6 |
0 |
0 |
| T426 |
159342 |
1 |
0 |
0 |
| T427 |
384378 |
2 |
0 |
0 |
| T428 |
209904 |
1 |
0 |
0 |
| T429 |
265887 |
2 |
0 |
0 |
| T430 |
346167 |
0 |
0 |
0 |