Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492610667	59360986	0	0
DepthKnown_A	492610667	492507272	0	0
RvalidKnown_A	492610667	492507272	0	0
WreadyKnown_A	492610667	492507272	0	0
gen_passthru_fifo.paramCheckPass	1014	1014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	59360986	0	0
T1	42264	3485	0	0
T2	64594	6191	0	0
T3	83706	9786	0	0
T4	88538	11318	0	0
T5	96760	57232	0	0
T6	109405	12191	0	0
T15	118850	13987	0	0
T33	93108	10504	0	0
T104	79399	8127	0	0
T105	73287	8656	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492610667	44620172	0	0
DepthKnown_A	492610667	492507272	0	0
RvalidKnown_A	492610667	492507272	0	0
WreadyKnown_A	492610667	492507272	0	0
gen_passthru_fifo.paramCheckPass	1014	1014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	44620172	0	0
T1	42264	1880	0	0
T2	64594	4534	0	0
T3	83706	6828	0	0
T4	88538	8040	0	0
T5	96760	28215	0	0
T6	109405	9642	0	0
T15	118850	9438	0	0
T33	93108	8408	0	0
T104	79399	6470	0	0
T105	73287	6136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492610667	41797121	0	0
DepthKnown_A	492610667	492507272	0	0
RvalidKnown_A	492610667	492507272	0	0
WreadyKnown_A	492610667	492507272	0	0
gen_passthru_fifo.paramCheckPass	1014	1014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	41797121	0	0
T1	42264	461	0	0
T2	64594	3692	0	0
T3	83706	4888	0	0
T4	88538	5600	0	0
T5	96760	6657	0	0
T6	109405	9369	0	0
T15	118850	9934	0	0
T33	93108	6186	0	0
T104	79399	5100	0	0
T105	73287	5628	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T36 T95 T96 
49         1/1              assign full_o = rready_i;
           Tests:       T36 T95 T96 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492610667	34916086	0	0
DepthKnown_A	492610667	492507272	0	0
RvalidKnown_A	492610667	492507272	0	0
WreadyKnown_A	492610667	492507272	0	0
gen_passthru_fifo.paramCheckPass	1014	1014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	34916086	0	0
T1	42264	353	0	0
T2	64594	3578	0	0
T3	83706	4699	0	0
T4	88538	5406	0	0
T5	96760	6036	0	0
T6	109405	8914	0	0
T15	118850	9627	0	0
T33	93108	6059	0	0
T104	79399	4986	0	0
T105	73287	5453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492610667	492507272	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584250107	90587	0	0
DepthKnown_A	584250107	584130702	0	0
RvalidKnown_A	584250107	584130702	0	0
WreadyKnown_A	584250107	584130702	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	90587	0	0
T1	42264	8	0	0
T2	64594	13	0	0
T3	83706	27	0	0
T4	88538	23	0	0
T5	96760	34	0	0
T6	109405	208	0	0
T15	118850	94	0	0
T33	93108	13	0	0
T104	79399	13	0	0
T105	73287	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584250107	92829	0	0
DepthKnown_A	584250107	584130702	0	0
RvalidKnown_A	584250107	584130702	0	0
WreadyKnown_A	584250107	584130702	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	92829	0	0
T1	42264	8	0	0
T2	64594	13	0	0
T3	83706	27	0	0
T4	88538	23	0	0
T5	96760	34	0	0
T6	109405	208	0	0
T15	118850	94	0	0
T33	93108	13	0	0
T104	79399	13	0	0
T105	73287	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584250107	52014	0	0
DepthKnown_A	584250107	584130702	0	0
RvalidKnown_A	584250107	584130702	0	0
WreadyKnown_A	584250107	584130702	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	52014	0	0
T1	42264	8	0	0
T2	64594	12	0	0
T3	83706	24	0	0
T4	88538	20	0	0
T5	96760	31	0	0
T6	109405	205	0	0
T15	118850	93	0	0
T33	93108	12	0	0
T104	79399	12	0	0
T105	73287	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584250107	52013	0	0
DepthKnown_A	584250107	584130702	0	0
RvalidKnown_A	584250107	584130702	0	0
WreadyKnown_A	584250107	584130702	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	52013	0	0
T1	42264	8	0	0
T2	64594	12	0	0
T3	83706	24	0	0
T4	88538	20	0	0
T5	96760	31	0	0
T6	109405	205	0	0
T15	118850	93	0	0
T33	93108	12	0	0
T104	79399	12	0	0
T105	73287	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584250107	38573	0	0
DepthKnown_A	584250107	584130702	0	0
RvalidKnown_A	584250107	584130702	0	0
WreadyKnown_A	584250107	584130702	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	38573	0	0
T2	64594	1	0	0
T3	83706	3	0	0
T4	88538	3	0	0
T5	96760	3	0	0
T6	109405	3	0	0
T15	118850	1	0	0
T25	0	3	0	0
T33	93108	1	0	0
T35	35762	0	0	0
T104	79399	1	0	0
T105	73287	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584250107	40816	0	0
DepthKnown_A	584250107	584130702	0	0
RvalidKnown_A	584250107	584130702	0	0
WreadyKnown_A	584250107	584130702	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	40816	0	0
T2	64594	1	0	0
T3	83706	3	0	0
T4	88538	3	0	0
T5	96760	3	0	0
T6	109405	3	0	0
T15	118850	1	0	0
T25	0	3	0	0
T33	93108	1	0	0
T35	35762	0	0	0
T104	79399	1	0	0
T105	73287	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584250107	584130702	0	0
T1	42264	42209	0	0
T2	64594	64543	0	0
T3	83706	83655	0	0
T4	88538	88487	0	0
T5	96760	96702	0	0
T6	109405	109350	0	0
T15	118850	118792	0	0
T33	93108	93050	0	0
T104	79399	79348	0	0
T105	73287	73236	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0