Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T93,T99,T249	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T94,T97,T98	Yes	T94,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T232,T206,T84	Yes	T232,T206,T84	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T78,T232,T206	Yes	T78,T232,T206	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T78,T233,T234	Yes	T78,T233,T234	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T37,T32,T45	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T36,T83,T84	Yes	T36,T83,T84	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T37,T32,T45	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T37,T32,T45	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T36,T83,T84	Yes	T36,T83,T84	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T37,T32,T45	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T36,T83,T84	Yes	T36,T83,T84	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T36,T83,T84	Yes	T36,T83,T84	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T36,T83,T281	Yes	T36,T83,T281	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T36,T83,T84	Yes	T36,T83,T84	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T36,*T83,*T84	Yes	T36,T83,T84	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T36,T83,T84	Yes	T36,T83,T84	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T92,T94,T97	Yes	T92,T94,T97	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T93,T99,T249	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T94,T97,T98	Yes	T92,T94,T97	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T84,T55,T56	Yes	T84,T55,T56	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T84,T55,T56	Yes	T84,T55,T56	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T84,T55,T56	Yes	T84,T55,T56	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T84,T55,T56	Yes	T84,T55,T56	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T84,T55,T56	Yes	T84,T55,T56	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T84,*T55,*T56	Yes	T84,T55,T56	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T84,T55,T56	Yes	T84,T55,T56	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T37,T32,T45	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T84,T55,T56	Yes	T84,T55,T56	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T84,T55,T56	Yes	T84,T55,T56	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T37,T32,T45	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T84,*T55,*T56	Yes	T84,T55,T56	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T37,T32,T45	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T84,T55,T56	Yes	T84,T55,T56	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T115,T83	Yes	T1,T115,T83	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T115,T417,T95	Yes	T115,T417,T95	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T418,T262	Yes	T72,T418,T262	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T72,T418,T262	Yes	T72,T418,T262	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T72,T418,T262	Yes	T72,T418,T262	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T72,T418,T262	Yes	T72,T418,T262	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T72,T418,T262	Yes	T72,T418,T262	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T418,T262,T419	Yes	T418,T262,T419	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T92,T93,T97	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T418,T262,T419	Yes	T72,T418,T262	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T262,*T420,*T421	Yes	T418,T262,T419	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T72,T418,T262	Yes	T72,T418,T262	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T97	Yes	T92,T93,T97	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T11,T219,T221	Yes	T11,T219,T221	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T422	Yes	T92,T93,T97	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T268,T72,T125	Yes	T268,T72,T125	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T268,T72,T125	Yes	T268,T72,T125	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T268,T72,T125	Yes	T268,T72,T125	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T268,T72,T125	Yes	T268,T72,T125	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T268,T72,T125	Yes	T268,T72,T125	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T268,T72,T125	Yes	T268,T72,T125	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T92,*T97,*T98	Yes	T92,T97,T98	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T268,T72,T125	Yes	T268,T72,T125	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T268,T72,T125	Yes	T268,T72,T125	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T98,T99,T399	Yes	T92,T98,T99	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T268,T125,T13	Yes	T268,T125,T13	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T268,T125,T423	Yes	T268,T72,T125	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T268,T125,T13	Yes	T268,T125,T13	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T97,T98	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T92,T97,T98	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T268,*T125,*T423	Yes	T268,T125,T423	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T268,T72,T125	Yes	T268,T72,T125	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T33,T7,T8	Yes	T33,T7,T8	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T33,T7,T8	Yes	T33,T7,T8	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T33,T7,T8	Yes	T33,T7,T8	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T33,T7,T8	Yes	T33,T7,T8	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T36,*T92,*T93	Yes	T36,T92,T93	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T33,T7,T8	Yes	T33,T7,T8	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T33,T7,T8	Yes	T33,T7,T8	INPUT
tl_usbdev_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T33,T7,T8	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T7,T8	Yes	T7,T8,T9	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T33,T7,T8	Yes	T7,T8,T9	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T36,*T97,*T98	Yes	T36,T92,T93	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T92,T94,T97	Yes	T92,T93,T97	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T7,*T8,*T9	Yes	T7,T8,T9	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T33,T7,T8	Yes	T33,T7,T8	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T223,*T93,*T97	Yes	T223,T93,T97	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T6,T37,T31	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T6,T5,T25	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T93,T97,T98	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T223,*T93,*T94	Yes	T223,T93,T97	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T223,T92,T93	Yes	T223,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T223,T92,T93	Yes	T223,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T223,T92,T93	Yes	T223,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T223,T92,T93	Yes	T223,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T223,T92,T93	Yes	T223,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T223,T92,T93	Yes	T223,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T223,T92,T93	Yes	T223,T92,T93	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T223,T93,T99	Yes	T223,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T223,T92,T97	Yes	T223,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T223,T92,T93	Yes	T223,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T223,T92,T93	Yes	T223,T92,T97	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T223,T97,T98	Yes	T223,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T97,T98,T99	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T223,*T92,*T93	Yes	T223,T92,T97	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T223,T92,T93	Yes	T223,T92,T93	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T3,T4,T105	Yes	T3,T4,T105	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T6,T37,T31	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T93,T94	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T72,T322,T323	Yes	T72,T322,T323	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T322,T323	Yes	T72,T322,T323	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T72,T322,T323	Yes	T72,T322,T323	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T72,T322,T323	Yes	T72,T322,T323	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T72,T322,T323	Yes	T72,T322,T323	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T223,*T92,*T93	Yes	T223,T92,T93	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T322,T323,T677	Yes	T322,T323,T677	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T72,T322,T323	Yes	T72,T322,T323	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T72,T322,T323	Yes	T72,T322,T323	INPUT
tl_hmac_i.d_error	Yes	Yes	T92,T93,T97	Yes	T93,T97,T98	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T322,T323,T677	Yes	T322,T323,T677	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T322,T323,T677	Yes	T322,T323,T677	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T72,T322,T323	Yes	T322,T323,T677	INPUT
tl_hmac_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T223,*T97,*T98	Yes	T223,T92,T93	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T72,*T322,*T323	Yes	T322,T323,T677	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T72,T322,T323	Yes	T72,T322,T323	INPUT
tl_kmac_o.d_ready	Yes	Yes	T6,T441,T37	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T441,T72,T456	Yes	T441,T72,T456	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T441,T37,T294	Yes	T441,T37,T294	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T441,T37,T294	Yes	T441,T37,T294	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T441,T72,T456	Yes	T441,T72,T456	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T441,T37,T294	Yes	T441,T37,T294	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T223,*T92,*T93	Yes	T223,T92,T93	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T441,T456,T457	Yes	T441,T456,T457	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T441,T37,T294	Yes	T441,T37,T294	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T441,T37,T294	Yes	T441,T37,T294	INPUT
tl_kmac_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T441,T37,T294	Yes	T441,T37,T294	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T441,T37,T294	Yes	T441,T37,T294	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T441,T37,T294	Yes	T441,T37,T200	INPUT
tl_kmac_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T223,*T92,*T97	Yes	T223,T92,T97	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T441,*T37,*T294	Yes	T441,T37,T200	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T441,T37,T294	Yes	T441,T37,T294	INPUT
tl_aes_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T224,*T92,*T93	Yes	T224,T92,T93	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	INPUT
tl_aes_i.d_error	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	INPUT
tl_aes_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T224,*T97,*T98	Yes	T224,T92,T93	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T414,*T415,*T258	Yes	T414,T415,T258	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T414,T415,T258	Yes	T414,T415,T258	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T223,*T93,*T97	Yes	T223,T93,T97	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T97,T99,T249	Yes	T97,T99,T399	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T156,T114,T153	Yes	T156,T114,T153	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T37,T32	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T6,T37,T32	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T223,*T97,*T98	Yes	T223,T93,T97	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T93,T97,T98	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T156,*T114,*T153	Yes	T156,T114,T153	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T259,T72,T156	Yes	T259,T72,T156	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T223,*T224,*T92	Yes	T223,T224,T92	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T259,T156,T117	Yes	T259,T156,T117	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T37,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T6,T37,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T223,*T224,*T97	Yes	T223,T224,T92	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T259,*T156,*T117	Yes	T259,T156,T117	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T259,T72,T156	Yes	T259,T72,T156	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T259,T72,T156	Yes	T259,T72,T156	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T223,*T92,*T93	Yes	T223,T92,T93	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T259,T156,T153	Yes	T259,T156,T153	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T37,T32	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T6,T37,T32	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T223,*T97,*T98	Yes	T223,T92,T93	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T97,T98	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T259,*T156,*T153	Yes	T259,T156,T153	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T72,T156,T153	Yes	T72,T156,T153	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T156,T153	Yes	T72,T156,T153	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T72,T156,T153	Yes	T72,T156,T153	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T72,T156,T153	Yes	T72,T156,T153	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T72,T156,T153	Yes	T72,T156,T153	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T223,*T92,*T93	Yes	T223,T92,T93	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T72,T156,T153	Yes	T72,T156,T153	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T72,T156,T153	Yes	T72,T156,T153	INPUT
tl_edn1_i.d_error	Yes	Yes	T97,T98,T99	Yes	T94,T97,T98	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T156,T153,T324	Yes	T156,T153,T324	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T153,T324,T244	Yes	T72,T156,T153	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T153,T324,T244	Yes	T72,T156,T153	INPUT
tl_edn1_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T223,*T94,*T97	Yes	T223,T92,T97	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T93,T97,T98	Yes	T97,T98,T99	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T156,*T153,*T324	Yes	T156,T153,T324	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T72,T156,T153	Yes	T72,T156,T153	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T93,*T97,*T98	Yes	T93,T97,T98	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T93,T97,T98	Yes	T92,T93,T97	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T97,T98,T99	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otbn_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T72,T210,T153	Yes	T72,T210,T153	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T210,T153	Yes	T72,T210,T153	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T72,T210,T153	Yes	T72,T210,T153	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T72,T210,T153	Yes	T72,T210,T153	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T72,T210,T153	Yes	T72,T210,T153	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T95,*T96,*T225	Yes	T95,T96,T225	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T72,T210,T153	Yes	T72,T210,T153	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T72,T210,T153	Yes	T72,T210,T153	INPUT
tl_otbn_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T210,T153,T324	Yes	T210,T153,T324	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T210,T153,T324	Yes	T210,T153,T324	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T72,T210,T153	Yes	T210,T153,T324	INPUT
tl_otbn_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T97,T98	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T95,*T96,*T225	Yes	T95,T96,T225	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T72,*T210,*T153	Yes	T210,T153,T324	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T72,T210,T153	Yes	T72,T210,T153	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T37,T294,T200	Yes	T37,T294,T200	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T37,T294,T200	Yes	T37,T294,T200	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T37,T294,T200	Yes	T37,T294,T200	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T37,T200,T72	Yes	T37,T200,T72	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T37,T294,T200	Yes	T37,T294,T200	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T223,*T92,*T93	Yes	T223,T92,T93	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T37,T294,T200	Yes	T37,T294,T200	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T37,T294,T200	Yes	T37,T294,T200	INPUT
tl_keymgr_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T37,T200,T194	Yes	T37,T200,T194	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T200,T194	Yes	T37,T200,T72	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T37,T200,T194	Yes	T37,T200,T72	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T93,T97,T98	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T223,*T97,*T98	Yes	T223,T92,T93	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T37,*T200,*T194	Yes	T37,T294,T200	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T37,T294,T200	Yes	T37,T294,T200	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T55,*T92,*T93	Yes	T55,T92,T93	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T55,T92,T93	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T72,T148,T206	Yes	T72,T148,T206	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T148,T206	Yes	T72,T148,T206	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T72,T148,T206	Yes	T72,T148,T206	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T72,T148,T206	Yes	T72,T148,T206	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T72,T148,T206	Yes	T72,T148,T206	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T447,*T92,*T93	Yes	T447,T92,T93	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T72,T148,T206	Yes	T72,T148,T206	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T72,T148,T206	Yes	T72,T148,T206	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T206,T287,T288	Yes	T206,T287,T288	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T148,T206,T203	Yes	T72,T148,T206	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T148,T206,T203	Yes	T72,T148,T206	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T97	Yes	T447,T92,T93	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T148,*T206,*T203	Yes	T148,T206,T203	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T72,T148,T206	Yes	T72,T148,T206	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T6,T37,T31	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range