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Module Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[1].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[2].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67 50.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67 50.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[5].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67 50.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67 50.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[8].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[9].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[10].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[11].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[12].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[13].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[14].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[15].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[16].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[17].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[18].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[19].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[20].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[21].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T33 T7 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T33 T7 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T7 T8 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T7 T8 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T33,T7
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT22,T23,T24
10CoveredT1,T2,T3
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T44,T213
11CoveredT9,T19,T20 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT23,T24,T44
01CoveredT1,T2,T3
10CoveredT23,T24,T44 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT23,T24,T44
11CoveredT23,T24,T44 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T19,T20 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT9,T19,T20 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T19,T20
11CoveredT22,T23,T24 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T9,T19,T20
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T7 T8 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T7 T8 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T7 T8 T9 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T7 T8 T9 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T8
10CoveredT22,T23,T44
11CoveredT22,T23,T44 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT7,T8,T9
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT9,T19,T20 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T19,T20 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T24,T44
11CoveredT9,T19,T20 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T24,T44 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T19,T20
11CoveredT22,T24,T44 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T9,T19,T20
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T22,T24,T44
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3900
CONT_ASSIGN51100.00
CONT_ASSIGN10200
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         0/1     ==>    assign ie = ie_i & ~attr_i.input_disable;
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78                          assign in_raw_o = ie ? inout_io : 1'bz;
79                          // input inversion
80                          assign in_o = attr_i.invert ^ in_raw_o;
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84                          assign out = out_i ^ attr_i.invert;
85                          assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92                          assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
93                          assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
94                          // pullup / pulldown termination
95                          assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
96                        `endif
97                        end else if (PadType == AnalogIn0 || PadType == AnalogIn1) begin : gen_analog
98                      
99                          //VCS coverage off
100                         // pragma coverage off
101                         logic unused_ana_sigs;
102        unreachable      assign unused_ana_sigs = ^{attr_i.invert,
103                                                    attr_i.virt_od_en,
104                                                    attr_i.drive_strength[0],
105                                                    attr_i.pull_en,
106                                                    attr_i.pull_select,
107                                                    out_i,
108                                                    oe_i,
109                                                    ie_i};
110                         //VCS coverage on
111                         // pragma coverage on
112                     
113                         assign inout_io = 1'bz; // explicitly make this tristate to avoid lint errors.
114        1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T33 T7 
115        1/1              assign in_o = in_raw_o;
           Tests:       T6 T33 T7 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions4250.00
Logical4250.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10Not Covered
11CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 114 2 1 50.00 



114            assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3900
CONT_ASSIGN51100.00
CONT_ASSIGN10200
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         0/1     ==>    assign ie = ie_i & ~attr_i.input_disable;
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78                          assign in_raw_o = ie ? inout_io : 1'bz;
79                          // input inversion
80                          assign in_o = attr_i.invert ^ in_raw_o;
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84                          assign out = out_i ^ attr_i.invert;
85                          assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92                          assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
93                          assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
94                          // pullup / pulldown termination
95                          assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
96                        `endif
97                        end else if (PadType == AnalogIn0 || PadType == AnalogIn1) begin : gen_analog
98                      
99                          //VCS coverage off
100                         // pragma coverage off
101                         logic unused_ana_sigs;
102        unreachable      assign unused_ana_sigs = ^{attr_i.invert,
103                                                    attr_i.virt_od_en,
104                                                    attr_i.drive_strength[0],
105                                                    attr_i.pull_en,
106                                                    attr_i.pull_select,
107                                                    out_i,
108                                                    oe_i,
109                                                    ie_i};
110                         //VCS coverage on
111                         // pragma coverage on
112                     
113                         assign inout_io = 1'bz; // explicitly make this tristate to avoid lint errors.
114        1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T33 T7 
115        1/1              assign in_o = in_raw_o;
           Tests:       T6 T33 T7 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions4250.00
Logical4250.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10Not Covered
11CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 114 2 1 50.00 



114            assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T10 T11 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T10 T11 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T10 T11 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T10 T11 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T10 T11 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T10 T11 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T10 T11 T12 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT10,T11,T12
01CoveredT6,T10,T11
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT6,T10,T11
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T44
11CoveredT6,T10,T11 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T44
01CoveredT1,T2,T3
10CoveredT22,T23,T44 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T44
11CoveredT22,T23,T44 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT6,T10,T11
11CoveredT22,T23,T24 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T10,T11 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT6,T10,T11 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T6,T10,T11
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T10 T11 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T10 T11 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T11 T12 T13 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T11 T12 T13 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T11 T12 T13 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T11 T12 T13 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T10 T11 T12 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T10,T11
01CoveredT6,T10,T11
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT11,T12,T13
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT21,T22,T23 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T44
10CoveredT21,T22,T23
11CoveredT22,T23,T24 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T23 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT21,T22,T23 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T21,T22,T23
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T10 T11 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T10 T11 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T11 T12 T13 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T11 T12 T13 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T11 T12 T13 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T11 T12 T13 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T10 T11 T12 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T11,T36
01CoveredT6,T10,T11
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT11,T13,T219
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T24,T44
11CoveredT21,T22,T23 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T24,T44 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT21,T22,T23
11CoveredT23,T24,T44 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T23 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T24,T44
11CoveredT21,T22,T23 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T23,T24,T44
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T21,T22,T23
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T10 T11 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T10 T11 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T11 T12 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T11 T12 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T11 T12 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T11 T12 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T10 T11 T12 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT11,T36,T95
01CoveredT6,T10,T11
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT6,T11,T13
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T44,T213
11CoveredT6,T38,T21 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT6,T38,T21
11CoveredT22,T23,T24 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T38,T21 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT6,T38,T21 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T6,T38,T21
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T10 T11 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T10 T11 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T10 T11 T12 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T10 T11 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T10 T11 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T10 T11 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T10 T46 T47 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T10,T11
01CoveredT10,T11,T12
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT10,T11,T12
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T44
11CoveredT6,T10,T11 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT6,T10,T11
11CoveredT22,T23,T24 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T10,T11 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT6,T10,T11 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T46,T47
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T6,T10,T11
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T10,T46,T47
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T10 T14 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T10 T14 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T10 T11 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T10 T11 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T10 T11 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T10 T11 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T10 T46 T47 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T10,T11
01CoveredT6,T10,T14
10CoveredT23,T24,T44
11CoveredT24,T44,T213 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT6,T10,T11
01CoveredT22,T23,T24
10CoveredT1,T2,T3
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT10,T11,T12 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT6,T10,T11
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT10,T11,T12
11CoveredT22,T23,T24 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT10,T11,T12 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T46,T47
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T10,T46,T47
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T15 T25 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T15 T25 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T14 T11 T12 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T14 T11 T12 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T14 T11 T12 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T14 T11 T12 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T15,T25
01CoveredT6,T15,T14
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT14,T11,T12
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT14,T11,T13 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T213 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT14,T11,T13
11CoveredT22,T23,T213 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T11,T13 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T213
11CoveredT14,T11,T13 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T213
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T14,T11,T13
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T15 T25 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T15 T25 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T15 T14 T11 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T15 T14 T11 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T15 T14 T11 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T15 T14 T11 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T15,T25
01CoveredT6,T15,T14
10CoveredT22,T23,T24
11CoveredT22,T23,T44 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT15,T14,T11
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT15,T14,T11 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T24,T44 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT15,T14,T11
11CoveredT22,T24,T44 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T14,T11 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T24,T44
11CoveredT15,T14,T11 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T24,T44
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T15,T14,T11
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T15 T25 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T15 T25 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T14 T11 T12 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T14 T11 T12 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T14 T11 T12 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T14 T11 T12 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T15,T25
01CoveredT6,T14,T11
10CoveredT22,T44,T213
11CoveredT22,T23,T44 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT14,T11,T12
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T24,T44
11CoveredT14,T11,T13 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T44,T215 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT14,T11,T13
11CoveredT22,T44,T215 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T11,T13 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T44,T215
11CoveredT14,T11,T13 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T44,T215
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T14,T11,T13
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T15 T25 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T15 T25 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T14 T11 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T14 T11 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T14 T11 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T14 T11 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT15,T25,T14
01CoveredT6,T14,T11
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT6,T14,T11
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT6,T14,T11 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT22,T23,T24 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT6,T14,T11
11CoveredT22,T23,T24 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T14,T11 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT6,T14,T11 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T6,T14,T11
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN5700
CONT_ASSIGN6411100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57         unreachable      assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T15 T25 
65                          // input inversion
66         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T15 T14 
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71         1/1              assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       64
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       66
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T15,T14
10CoveredT22,T23,T24
11CoveredT22,T23,T24 

 LINE       71
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 64 2 2 100.00
TERNARY 71 2 2 100.00 



64             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



71             assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                               -1-  
                                                               ==>  
                                                               ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN5700
CONT_ASSIGN6411100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57         unreachable      assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T25 T14 
65                          // input inversion
66         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T25 T14 
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71         1/1              assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       64
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       66
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T25,T14
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT22,T23,T44 

 LINE       71
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 64 2 2 100.00
TERNARY 71 2 2 100.00 



64             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



71             assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                               -1-  
                                                               ==>  
                                                               ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T6 T25 T30 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T6 T25 T30 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T16 T17 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T25 T16 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T25 T16 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T25 T16 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT22,T23,T24
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T25,T30
10CoveredT22,T23,T24
11CoveredT23,T44,T213 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T24
10CoveredT6,T16,T17
11CoveredT22,T23,T24 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT25,T26,T21
10CoveredT22,T23,T24
11CoveredT1,T2,T3 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT22,T23,T24
01CoveredT1,T2,T3
10CoveredT18,T48,T49 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T24
11CoveredT18,T48,T49 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T44 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT1,T2,T3
11CoveredT22,T23,T44 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT25,T26,T21
1CoveredT1,T2,T3 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT25,T26,T21
10CoveredT22,T23,T44
11CoveredT1,T2,T3 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T24
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T22,T23,T24 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T44
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T25,T26,T21 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T22,T23,T24
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1014 1014 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T33 1 1 0 0
T104 1 1 0 0
T105 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%