Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T6,T37,T31	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T130,T112,T36	Yes	T130,T112,T36	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T130,T112,T36	Yes	T130,T112,T36	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T130,T72,T112	Yes	T130,T72,T112	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T130,T72,T186	Yes	T130,T72,T186	INPUT
tl_uart0_i.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T130,T36,T320	Yes	T130,T36,T320	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T130,T186,T36	Yes	T130,T72,T186	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T130,T186,T36	Yes	T130,T72,T186	INPUT
tl_uart0_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T36,*T55,*T448	Yes	T36,T55,T448	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T130,*T36,*T320	Yes	T130,T36,T320	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T130,T72,T186	Yes	T130,T72,T186	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T131,T36,T132	Yes	T131,T36,T132	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T131,T36,T132	Yes	T131,T36,T132	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T131,T72,T186	Yes	T131,T72,T186	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T131,T72,T186	Yes	T131,T72,T186	INPUT
tl_uart1_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T94	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T131,T36,T132	Yes	T131,T36,T132	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T131,T186,T36	Yes	T131,T72,T186	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T131,T186,T36	Yes	T131,T72,T186	INPUT
tl_uart1_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T94	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T36,*T92,*T94	Yes	T36,T92,T93	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T94	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T131,*T36,*T132	Yes	T131,T36,T132	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T131,T72,T186	Yes	T131,T72,T186	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T29,T64,T36	Yes	T29,T64,T36	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T29,T64,T36	Yes	T29,T64,T36	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T29,T72,T64	Yes	T29,T72,T64	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T29,T72,T64	Yes	T29,T72,T64	INPUT
tl_uart2_i.d_error	Yes	Yes	T97,T98,T99	Yes	T92,T97,T98	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T29,T64,T36	Yes	T29,T64,T36	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T64,T186	Yes	T29,T72,T64	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T29,T64,T186	Yes	T29,T72,T64	INPUT
tl_uart2_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T36,*T97,*T98	Yes	T36,T92,T97	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T29,*T64,*T36	Yes	T29,T64,T36	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T29,T72,T64	Yes	T29,T72,T64	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T39,T65,T36	Yes	T39,T65,T36	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T39,T65,T36	Yes	T39,T65,T36	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T39,T65,T72	Yes	T39,T65,T72	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T39,T65,T72	Yes	T39,T65,T72	INPUT
tl_uart3_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T39,T65,T36	Yes	T39,T65,T36	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T65,T186	Yes	T39,T65,T72	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T39,T65,T186	Yes	T39,T65,T72	INPUT
tl_uart3_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T36,*T97,*T98	Yes	T36,T92,T93	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T39,*T65,*T36	Yes	T39,T65,T36	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T39,T65,T72	Yes	T39,T65,T72	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T58,T268,T59	Yes	T58,T268,T59	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T58,T268,T59	Yes	T58,T268,T59	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T58,T268,T59	Yes	T58,T268,T59	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T58,T268,T59	Yes	T58,T268,T59	INPUT
tl_i2c0_i.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T58,T59,T329	Yes	T58,T59,T329	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T58,T268,T59	Yes	T58,T268,T59	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T58,T268,T59	Yes	T58,T268,T59	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T223,*T97,*T98	Yes	T223,T92,T93	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T93,T97,T98	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T58,*T268,*T59	Yes	T58,T268,T59	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T58,T268,T59	Yes	T58,T268,T59	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T268,T60,T329	Yes	T268,T60,T329	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T268,T60,T329	Yes	T268,T60,T329	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T268,T60,T72	Yes	T268,T60,T72	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T268,T60,T72	Yes	T268,T60,T72	INPUT
tl_i2c1_i.d_error	Yes	Yes	T97,T98,T249	Yes	T93,T97,T98	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T60,T329,T13	Yes	T60,T329,T13	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T268,T60,T186	Yes	T268,T60,T72	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T268,T60,T186	Yes	T268,T60,T72	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T223,*T97,*T98	Yes	T223,T92,T93	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T268,*T60,*T329	Yes	T268,T60,T329	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T268,T60,T72	Yes	T268,T60,T72	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T268,T62,T329	Yes	T268,T62,T329	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T268,T62,T329	Yes	T268,T62,T329	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T268,T62,T72	Yes	T268,T62,T72	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T268,T62,T72	Yes	T268,T62,T72	INPUT
tl_i2c2_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T62,T329,T13	Yes	T62,T329,T13	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T268,T62,T186	Yes	T268,T62,T72	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T268,T62,T186	Yes	T268,T62,T72	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T223,*T92,*T93	Yes	T223,T92,T93	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T268,*T62,*T329	Yes	T268,T62,T329	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T268,T62,T72	Yes	T268,T62,T72	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T3,T125,T13	Yes	T3,T125,T13	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T3,T125,T13	Yes	T3,T125,T13	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T3,T72,T125	Yes	T3,T72,T125	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T3,T72,T125	Yes	T3,T72,T125	INPUT
tl_pattgen_i.d_error	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T3,T125,T13	Yes	T3,T125,T13	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T125,T13	Yes	T3,T72,T125	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T3,T125,T13	Yes	T3,T72,T125	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T97,T98	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T93,*T94,T97	Yes	T92,T93,T97	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T3,*T125,*T13	Yes	T3,T125,T13	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T3,T72,T125	Yes	T3,T72,T125	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T34,T127,T135	Yes	T34,T127,T135	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T34,T127,T135	Yes	T34,T127,T135	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T34,T72,T127	Yes	T34,T72,T127	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T34,T72,T127	Yes	T34,T72,T127	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T34,T127,T135	Yes	T34,T127,T135	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T127,T135	Yes	T34,T72,T127	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T34,T127,T135	Yes	T34,T72,T127	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T92,*T97,*T98	Yes	T92,T93,T97	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T34,*T127,*T135	Yes	T34,T127,T135	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T34,T72,T127	Yes	T34,T72,T127	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_error	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T14,T28,T329	Yes	T14,T28,T329	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T14,T28,T329	Yes	T4,T14,T28	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T14,T28,T329	Yes	T4,T14,T28	INPUT
tl_gpio_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T223,*T93,*T97	Yes	T223,T92,T93	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T14	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T15,T14,T11	Yes	T15,T14,T11	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T15,T14,T11	Yes	T15,T14,T11	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T15,T14,T11	Yes	T15,T14,T11	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T15,T14,T11	Yes	T15,T14,T11	INPUT
tl_spi_device_i.d_error	Yes	Yes	T92,T93,T97	Yes	T93,T97,T98	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T15,T11,T12	Yes	T15,T11,T12	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T14,T11	Yes	T15,T14,T11	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T15,T14,T11	Yes	T15,T11,T12	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T93,T97,T98	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T94,*T97,*T98	Yes	T92,T93,T97	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T15,*T14,*T11	Yes	T15,T14,T11	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T15,T14,T11	Yes	T15,T14,T11	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T124,T236,T290	Yes	T124,T236,T290	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T124,T236,T290	Yes	T124,T236,T290	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T124,T236,T72	Yes	T124,T236,T72	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T124,T236,T72	Yes	T124,T236,T72	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T124,T290,T125	Yes	T124,T290,T125	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T124,T236,T290	Yes	T124,T236,T72	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T124,T236,T290	Yes	T124,T236,T72	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T92,*T97,*T98	Yes	T92,T93,T97	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T124,*T236,*T290	Yes	T124,T236,T290	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T124,T236,T72	Yes	T124,T236,T72	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T25	Yes	T4,T6,T25	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T25	Yes	T4,T6,T25	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T6,T25	Yes	T4,T6,T25	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T6,T25	Yes	T4,T6,T25	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T25	Yes	T4,T6,T25	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T25	Yes	T4,T6,T25	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T25	Yes	T4,T6,T25	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T94	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T92,*T94,*T97	Yes	T92,T93,T97	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T25	Yes	T4,T6,T25	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T6,T25	Yes	T4,T6,T25	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T32,T45	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T37,T32,T45	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T98	Yes	T92,T93,T97	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T29,T130,T131	Yes	T29,T130,T131	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T29,T130,T131	Yes	T29,T130,T131	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T29,T130,T131	Yes	T29,T130,T131	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T29,T130	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T37,T29,T130	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T93,T97,T98	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T224,*T93,*T97	Yes	T177,T178,T224	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T29,*T130,*T131	Yes	T29,T130,T131	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T92,T93,T97	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T93,T97,T98	Yes	T92,T93,T97	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T177,*T178,*T179	Yes	T177,T178,T179	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T94,T97	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T180,*T37,*T181	Yes	T180,T37,T181	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T32,T45,T78	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T92,T93,T97	Yes	T93,T97,T98	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T32,T45,T78	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T93,T97,T98	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T32,T45,T78	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T5,T180,T37	Yes	T5,T180,T37	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T5,T180,T37	Yes	T5,T180,T37	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T5,T180,T37	Yes	T5,T180,T37	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T5,T180,T37	Yes	T5,T180,T37	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T92,T93,T94	Yes	T92,T97,T98	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T37,T201,T195	Yes	T5,T180,T37	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T201,T195,T192	Yes	T201,T195,T72	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T180,T37,T201	Yes	T5,T180,T37	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T93,T94	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T84,*T315,*T316	Yes	T84,T315,T316	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T97,T98	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T37,*T201,*T195	Yes	T5,T180,T37	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T5,T180,T37	Yes	T5,T180,T37	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T172,T158,T125	Yes	T172,T158,T125	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T172,T158,T125	Yes	T72,T172,T158	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T37,T32,T45	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T98	Yes	T92,T93,T97	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T37,*T32,*T45	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T224,*T92,*T97	Yes	T224,T92,T93	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T45,*T78,*T79	Yes	T45,T78,T79	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T148,T205,T203	Yes	T148,T205,T203	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T148,T205,T203	Yes	T148,T205,T203	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T72,T148,T205	Yes	T72,T148,T205	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T72,T148,T205	Yes	T72,T148,T205	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T93,T97,T98	Yes	T93,T97,T98	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T148,T205,T203	Yes	T148,T205,T203	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T148,T205,T203	Yes	T72,T148,T205	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T148,T205,T203	Yes	T72,T148,T205	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T93,T97,T98	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T92,T93,T97	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T92,T93,T97	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T148,*T205,*T203	Yes	T148,T205,T203	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T72,T148,T205	Yes	T72,T148,T205	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T37,T31,T32	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T235,T37,T31	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T45,T78,T79	Yes	T45,T78,T79	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T95,*T55,*T448	Yes	T95,T55,T448	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T224,*T93,*T97	Yes	T56,T683,T447	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T235,*T45,*T78	Yes	T235,T45,T78	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T235,T45,T78	Yes	T235,T45,T78	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T30,T16,T18	Yes	T30,T16,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T30,T16,T18	Yes	T30,T16,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T30,T16,T18	Yes	T30,T16,T18	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T30,T16,T18	Yes	T30,T16,T18	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T92,T97,T98	Yes	T97,T98,T99	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T30,T16,T18	Yes	T30,T16,T18	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T18,T67	Yes	T16,T18,T67	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T30,T16,T18	Yes	T30,T16,T18	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T36,*T97,*T98	Yes	T36,T92,T97	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T97,T98,T99	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T16,*T18,*T67	Yes	T30,T16,T18	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T30,T16,T18	Yes	T30,T16,T18	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T139,T69,T329	Yes	T139,T69,T329	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T139,T69,T329	Yes	T139,T69,T329	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T72,T139,T69	Yes	T72,T139,T69	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T72,T139,T69	Yes	T72,T139,T69	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T93,T97,T98	Yes	T93,T94,T97	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T139,T69,T329	Yes	T139,T69,T329	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T139,T69,T329	Yes	T72,T139,T69	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T139,T69,T119	Yes	T72,T139,T69	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T97	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T224,*T93,*T94	Yes	T224,T92,T93	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T139,*T69,*T329	Yes	T139,T69,T329	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T72,T139,T69	Yes	T72,T139,T69	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T36,*T84,*T95	Yes	T36,T84,T95	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T92,T94,T97	Yes	T94,T97,T98	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T92,T94,T97	Yes	T92,T94,T97	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T37,T32	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T6,T37,T32	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T94,*T97,*T98	Yes	T94,T97,T98	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T92,T94,T97	Yes	T92,T94,T97	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T92,*T93,*T94	Yes	T92,T94,T97	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range