Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1014	1014	0	0
OutputsKnown_A	122580651	121931276	0	0
gen_no_flops.OutputDelay_A	122580651	121931276	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122580651	121931276	0	0
T1	10949	10512	0	0
T2	16423	15872	0	0
T3	20788	20459	0	0
T4	24012	23491	0	0
T5	24112	23590	0	0
T6	27742	27125	0	0
T15	29610	28893	0	0
T33	23438	22714	0	0
T104	19888	19425	0	0
T105	18382	17958	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122580651	121931276	0	0
T1	10949	10512	0	0
T2	16423	15872	0	0
T3	20788	20459	0	0
T4	24012	23491	0	0
T5	24112	23590	0	0
T6	27742	27125	0	0
T15	29610	28893	0	0
T33	23438	22714	0	0
T104	19888	19425	0	0
T105	18382	17958	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1014	1014	0	0
OutputsKnown_A	122580651	121931276	0	0
gen_no_flops.OutputDelay_A	122580651	121931276	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122580651	121931276	0	0
T1	10949	10512	0	0
T2	16423	15872	0	0
T3	20788	20459	0	0
T4	24012	23491	0	0
T5	24112	23590	0	0
T6	27742	27125	0	0
T15	29610	28893	0	0
T33	23438	22714	0	0
T104	19888	19425	0	0
T105	18382	17958	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122580651	121931276	0	0
T1	10949	10512	0	0
T2	16423	15872	0	0
T3	20788	20459	0	0
T4	24012	23491	0	0
T5	24112	23590	0	0
T6	27742	27125	0	0
T15	29610	28893	0	0
T33	23438	22714	0	0
T104	19888	19425	0	0
T105	18382	17958	0	0