Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.26 99.26

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 99.02 99.02
tb.dut.top_earlgrey.u_edn0 99.17 99.17


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 99.17


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 99.17


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1210 1201 99.26
Total Bits 0->1 605 602 99.50
Total Bits 1->0 605 599 99.01

Ports 78 74 94.87
Port Bits 1210 1201 99.26
Port Bits 0->1 605 602 99.50
Port Bits 1->0 605 599 99.01

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T6,T37,T31 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T259,T72,T156 Yes T259,T72,T156 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T259,T72,T156 Yes T259,T72,T156 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T92,*T93,*T97 Yes T92,T93,T97 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T223,*T92,*T93 Yes T223,T92,T93 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T92,T93,T97 Yes T92,T93,T97 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T92,T93,T97 Yes T92,T93,T97 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T92,T97,T98 Yes T92,T94,T97 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T259,T156,T153 Yes T259,T156,T153 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T6,T37,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T37,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T92,T97,T98 Yes T92,T97,T98 OUTPUT
tl_o.d_source[5:0] Yes Yes *T223,*T94,*T97 Yes T223,T92,T93 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T92,T93,T97 Yes T92,T97,T98 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T259,*T156,*T153 Yes T259,T156,T153 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T37,T200,T194 Yes T37,T200,T194 INPUT
edn_i[1].edn_req Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
edn_i[2].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T441,T245,T149 Yes T441,T245,T149 INPUT
edn_i[4].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T200,T194,T295 Yes T200,T194,T295 OUTPUT
edn_o[0].edn_fips Yes Yes T153,T253,T458 Yes T153,T324,T245 OUTPUT
edn_o[0].edn_ack Yes Yes T37,T200,T194 Yes T37,T200,T194 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[1].edn_fips No No Yes T175,T144,T176 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T3,T5 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_fips Yes Yes T140,T141,T142 Yes T143,T144,T140 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T441,T245,T149 Yes T441,T245,T149 OUTPUT
edn_o[3].edn_fips No No Yes T245,T149,T13 OUTPUT
edn_o[3].edn_ack Yes Yes T441,T245,T149 Yes T441,T245,T149 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T37,T201,T79 Yes T2,T3,T104 OUTPUT
edn_o[4].edn_fips No No Yes T176,T458,T645 OUTPUT
edn_o[4].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T253,T458,T646 Yes T245,T149,T253 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T153,T253,T458 Yes T153,T324,T245 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T3,T6,T5 Yes T3,T4,T6 OUTPUT
edn_o[7].edn_fips Yes Yes T153,T253,T140 Yes T153,T244,T245 OUTPUT
edn_o[7].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T6,T37,T32 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T153,T140,T647 Yes T153,T324,T244 INPUT
csrng_cmd_i.genbits_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T259,T154,T253 Yes T259,T154,T253 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T259,T72,T101 Yes T259,T72,T101 INPUT
alert_rx_i[0].ping_n Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_rx_i[0].ping_p Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T72,T101,T102 Yes T72,T101,T102 INPUT
alert_rx_i[1].ping_n Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_rx_i[1].ping_p Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T259,T72,T101 Yes T259,T72,T101 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T72,T101,T102 Yes T72,T101,T102 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T335,T329,T336 Yes T335,T329,T336 OUTPUT
intr_edn_fatal_err_o Yes Yes T329,T330,T331 Yes T329,T330,T331 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 714 707 99.02
Total Bits 0->1 357 354 99.16
Total Bits 1->0 357 353 98.88

Ports 50 48 96.00
Port Bits 714 707 99.02
Port Bits 0->1 357 354 99.16
Port Bits 1->0 357 353 98.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T6,T37,T31 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T6,T37,T31 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T72,T156,T153 Yes T72,T156,T153 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T72,T156,T153 Yes T72,T156,T153 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T72,T156,T153 Yes T72,T156,T153 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T72,T156,T153 Yes T72,T156,T153 INPUT
tl_i.a_mask[3:0] Yes Yes T72,T156,T153 Yes T72,T156,T153 INPUT
tl_i.a_address[6:0] Yes Yes *T92,*T97,*T98 Yes T92,T97,T98 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T72,T156,T153 Yes T72,T156,T153 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T72,*T156,*T153 Yes T72,T156,T153 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T72,*T156,*T153 Yes T72,T156,T153 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T223,*T92,*T93 Yes T223,T92,T93 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T93,T97,T98 Yes T93,T97,T98 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T92,T93,T97 Yes T92,T93,T97 INPUT
tl_i.a_valid Yes Yes T72,T156,T153 Yes T72,T156,T153 INPUT
tl_o.a_ready Yes Yes T72,T156,T153 Yes T72,T156,T153 OUTPUT
tl_o.d_error Yes Yes T97,T98,T99 Yes T94,T97,T98 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T156,T153,T324 Yes T156,T153,T324 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T153,T324,T244 Yes T72,T156,T153 OUTPUT
tl_o.d_data[31:0] Yes Yes T153,T324,T244 Yes T72,T156,T153 OUTPUT
tl_o.d_sink Yes Yes T92,T97,T98 Yes T92,T97,T98 OUTPUT
tl_o.d_source[5:0] Yes Yes *T223,*T94,*T97 Yes T223,T92,T97 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T93,T97,T98 Yes T97,T98,T99 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T156,*T153,*T324 Yes T156,T153,T324 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T72,T156,T153 Yes T72,T156,T153 OUTPUT
edn_i[0].edn_req Yes Yes T153,T324,T245 Yes T153,T324,T245 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T153,T324,T245 Yes T153,T324,T245 OUTPUT
edn_o[0].edn_fips Yes Yes T153,T253,T458 Yes T153,T324,T245 OUTPUT
edn_o[0].edn_ack Yes Yes T153,T324,T245 Yes T153,T324,T245 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T153,T324,T244 Yes T153,T324,T244 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T153,T324,T154 Yes T153,T324,T244 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T153,T324,T244 Yes T153,T324,T244 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T153,T324,T154 Yes T153,T324,T154 INPUT
csrng_cmd_i.genbits_fips No No Yes T153,T647,T648 INPUT
csrng_cmd_i.genbits_valid Yes Yes T153,T324,T244 Yes T153,T324,T244 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T153,T324,T244 Yes T153,T324,T244 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T253,T458,T646 Yes T253,T458,T646 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T72,T101,T102 Yes T72,T101,T102 INPUT
alert_rx_i[0].ping_n Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_rx_i[0].ping_p Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T72,T101,T102 Yes T72,T101,T102 INPUT
alert_rx_i[1].ping_n Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_rx_i[1].ping_p Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T72,T101,T102 Yes T72,T101,T102 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T72,T101,T102 Yes T72,T101,T102 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T335,T329,T336 Yes T335,T329,T336 OUTPUT
intr_edn_fatal_err_o Yes Yes T329,T330,T331 Yes T329,T330,T331 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 73 93.59
Total Bits 1208 1198 99.17
Total Bits 0->1 604 601 99.50
Total Bits 1->0 604 597 98.84

Ports 78 73 93.59
Port Bits 1208 1198 99.17
Port Bits 0->1 604 601 99.50
Port Bits 1->0 604 597 98.84

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T6,T37,T31 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T259,T72,T156 Yes T259,T72,T156 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T259,T72,T156 Yes T259,T72,T156 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T92,*T93,*T97 Yes T92,T93,T97 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T223,*T92,*T93 Yes T223,T92,T93 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T92,T93,T97 Yes T92,T93,T97 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T92,T97,T98 Yes T92,T97,T98 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T92,T97,T98 Yes T92,T97,T98 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T259,T156,T153 Yes T259,T156,T153 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T6,T37,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T37,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T92,T97,T98 Yes T92,T97,T98 OUTPUT
tl_o.d_source[5:0] Yes Yes *T223,*T97,*T98 Yes T223,T92,T93 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T92,T93,T97 Yes T92,T97,T98 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T259,*T156,*T153 Yes T259,T156,T153 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T37,T200,T194 Yes T37,T200,T194 INPUT
edn_i[1].edn_req Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
edn_i[2].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T441,T245,T149 Yes T441,T245,T149 INPUT
edn_i[4].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T200,T194,T295 Yes T200,T194,T295 OUTPUT
edn_o[0].edn_fips No No Yes T245,T143,T149 OUTPUT
edn_o[0].edn_ack Yes Yes T37,T200,T194 Yes T37,T200,T194 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[1].edn_fips No No Yes T175,T144,T176 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T3,T5 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_fips Yes Yes T140,T141,T142 Yes T143,T144,T140 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T441,T245,T149 Yes T441,T245,T149 OUTPUT
edn_o[3].edn_fips No No Yes T245,T149,T13 OUTPUT
edn_o[3].edn_ack Yes Yes T441,T245,T149 Yes T441,T245,T149 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T37,T201,T79 Yes T2,T3,T104 OUTPUT
edn_o[4].edn_fips No No Yes T176,T458,T645 OUTPUT
edn_o[4].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T253,T458,T646 Yes T245,T149,T253 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T153,T253,T458 Yes T153,T324,T245 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T3,T6,T5 Yes T3,T4,T6 OUTPUT
edn_o[7].edn_fips Yes Yes T153,T253,T140 Yes T153,T244,T245 OUTPUT
edn_o[7].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T6,T37,T32 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T153,T140,T647 Yes T153,T324,T244 INPUT
csrng_cmd_i.genbits_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T259,T154,T253 Yes T259,T154,T253 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T259,T72,T101 Yes T259,T72,T101 INPUT
alert_rx_i[0].ping_n Yes Yes T101,T102,T103 Yes T101,T102,T254 INPUT
alert_rx_i[0].ping_p Yes Yes T101,T102,T254 Yes T101,T102,T103 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T72,T101,T102 Yes T72,T101,T102 INPUT
alert_rx_i[1].ping_n Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_rx_i[1].ping_p Yes Yes T101,T102,T103 Yes T101,T102,T103 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T259,T72,T101 Yes T259,T72,T101 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T72,T101,T102 Yes T72,T101,T102 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T335,T329,T336 Yes T335,T329,T336 OUTPUT
intr_edn_fatal_err_o Yes Yes T329,T330,T331 Yes T329,T330,T331 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%