CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 388089 | 1 | T276 | 348 | T475 | 1 | T274 | 436 | ||||
rising | 388186 | 1 | T276 | 349 | T475 | 1 | T274 | 436 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1094198 | 1 | T276 | 1472 | T475 | 2 | T274 | 1718 | ||||
auto[1] | 9519266 | 1 | T91 | 334 | T92 | 292 | T93 | 4756 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 343645 | 1 | T409 | 1 | T276 | 321 | T274 | 471 | ||||
rising | 343710 | 1 | T409 | 1 | T276 | 320 | T274 | 470 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1222092 | 1 | T409 | 2 | T276 | 1308 | T274 | 1990 | ||||
auto[1] | 10307404 | 1 | T91 | 240 | T92 | 364 | T93 | 4362 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 691186 | 1 | T93 | 4 | T180 | 1 | T276 | 752 | ||||
rising | 691251 | 1 | T93 | 4 | T180 | 2 | T276 | 752 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1109905 | 1 | T93 | 4 | T180 | 2 | T276 | 1512 | ||||
auto[1] | 9631136 | 1 | T91 | 274 | T92 | 256 | T93 | 4772 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6621 | 1 | T97 | 1 | T274 | 1 | T536 | 1 | ||||
rising | 6655 | 1 | T97 | 1 | T274 | 1 | T536 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 174603 | 1 | T91 | 6 | T92 | 2 | T93 | 74 | ||||
auto[1] | 13575 | 1 | T97 | 1 | T274 | 1 | T536 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5418 | 1 | T560 | 1 | T557 | 2 | T567 | 1 | ||||
rising | 5453 | 1 | T560 | 1 | T557 | 2 | T567 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 186650 | 1 | T91 | 9 | T92 | 4 | T93 | 95 | ||||
auto[1] | 8374 | 1 | T560 | 1 | T557 | 2 | T567 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3282 | 1 | T572 | 1 | T557 | 2 | T574 | 2 | ||||
rising | 3303 | 1 | T572 | 1 | T557 | 2 | T574 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 185470 | 1 | T91 | 5 | T92 | 5 | T93 | 107 | ||||
auto[1] | 3522 | 1 | T572 | 1 | T557 | 2 | T574 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6126 | 1 | T557 | 1 | T558 | 1 | T461 | 8 | ||||
rising | 6169 | 1 | T557 | 1 | T558 | 1 | T461 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 167313 | 1 | T91 | 4 | T92 | 2 | T93 | 91 | ||||
auto[1] | 14744 | 1 | T557 | 1 | T558 | 1 | T461 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4192 | 1 | T409 | 56 | T557 | 4 | T574 | 1 | ||||
rising | 4218 | 1 | T409 | 56 | T557 | 4 | T574 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 180977 | 1 | T91 | 1 | T92 | 3 | T93 | 76 | ||||
auto[1] | 4778 | 1 | T409 | 60 | T557 | 4 | T574 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7881 | 1 | T274 | 1 | T563 | 1 | T536 | 1 | ||||
rising | 7923 | 1 | T274 | 1 | T563 | 1 | T536 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 173554 | 1 | T91 | 4 | T92 | 5 | T93 | 108 | ||||
auto[1] | 16241 | 1 | T274 | 1 | T563 | 1 | T536 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6935 | 1 | T557 | 2 | T574 | 1 | T566 | 2 | ||||
rising | 6980 | 1 | T557 | 2 | T574 | 1 | T566 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 177727 | 1 | T91 | 6 | T92 | 10 | T93 | 109 | ||||
auto[1] | 15437 | 1 | T557 | 2 | T574 | 1 | T566 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5894 | 1 | T560 | 2 | T557 | 4 | T566 | 1 | ||||
rising | 5938 | 1 | T560 | 3 | T557 | 4 | T566 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 173455 | 1 | T91 | 10 | T92 | 6 | T93 | 113 | ||||
auto[1] | 12612 | 1 | T560 | 3 | T557 | 5 | T566 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6608 | 1 | T560 | 1 | T557 | 1 | T573 | 1 | ||||
rising | 6656 | 1 | T274 | 1 | T560 | 1 | T557 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 184544 | 1 | T91 | 3 | T92 | 7 | T93 | 113 | ||||
auto[1] | 13716 | 1 | T274 | 1 | T560 | 1 | T557 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4962 | 1 | T274 | 1 | T560 | 2 | T569 | 1 | ||||
rising | 4990 | 1 | T274 | 1 | T560 | 2 | T569 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 179740 | 1 | T91 | 6 | T92 | 7 | T93 | 112 | ||||
auto[1] | 7389 | 1 | T274 | 1 | T560 | 2 | T569 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4238 | 1 | T557 | 2 | T574 | 1 | T562 | 2 | ||||
rising | 4262 | 1 | T557 | 2 | T574 | 1 | T562 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 182601 | 1 | T91 | 4 | T92 | 6 | T93 | 95 | ||||
auto[1] | 5401 | 1 | T557 | 2 | T574 | 1 | T562 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 14855 | 1 | T274 | 5 | T563 | 3 | T560 | 2 | ||||
rising | 14878 | 1 | T274 | 5 | T563 | 3 | T560 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1457579 | 1 | T91 | 29 | T92 | 48 | T93 | 609 | ||||
auto[1] | 15526 | 1 | T274 | 5 | T563 | 3 | T560 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5735 | 1 | T274 | 3 | T566 | 2 | T689 | 3 | ||||
rising | 5773 | 1 | T274 | 3 | T566 | 2 | T689 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 175976 | 1 | T91 | 4 | T92 | 7 | T93 | 86 | ||||
auto[1] | 11342 | 1 | T274 | 3 | T566 | 2 | T689 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7560 | 1 | T536 | 1 | T473 | 66 | T568 | 1 | ||||
rising | 7602 | 1 | T536 | 1 | T473 | 66 | T568 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 168091 | 1 | T91 | 4 | T92 | 5 | T93 | 102 | ||||
auto[1] | 20939 | 1 | T536 | 1 | T473 | 110 | T568 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2144 | 1 | T562 | 1 | T558 | 2 | T689 | 3 | ||||
rising | 2168 | 1 | T562 | 1 | T558 | 2 | T689 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 184755 | 1 | T91 | 8 | T92 | 3 | T93 | 96 | ||||
auto[1] | 2281 | 1 | T562 | 2 | T558 | 2 | T689 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6885 | 1 | T97 | 1 | T409 | 61 | T563 | 1 | ||||
rising | 6929 | 1 | T97 | 1 | T409 | 61 | T563 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 179615 | 1 | T91 | 9 | T92 | 4 | T93 | 103 | ||||
auto[1] | 13786 | 1 | T97 | 1 | T409 | 103 | T563 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8370 | 1 | T563 | 1 | T557 | 2 | T574 | 1 | ||||
rising | 8408 | 1 | T563 | 1 | T557 | 2 | T574 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 176747 | 1 | T91 | 5 | T92 | 10 | T93 | 103 | ||||
auto[1] | 16771 | 1 | T563 | 1 | T557 | 2 | T574 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6610 | 1 | T536 | 1 | T572 | 1 | T435 | 1 | ||||
rising | 6660 | 1 | T536 | 1 | T572 | 1 | T435 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 171242 | 1 | T91 | 6 | T92 | 8 | T93 | 90 | ||||
auto[1] | 13502 | 1 | T536 | 1 | T572 | 1 | T435 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5784 | 1 | T562 | 2 | T690 | 44 | T689 | 1 | ||||
rising | 5816 | 1 | T562 | 2 | T690 | 45 | T689 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 186788 | 1 | T91 | 6 | T92 | 6 | T93 | 86 | ||||
auto[1] | 8755 | 1 | T562 | 2 | T690 | 49 | T689 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3114 | 1 | T572 | 1 | T557 | 1 | T574 | 1 | ||||
rising | 3140 | 1 | T572 | 1 | T557 | 1 | T574 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 203852 | 1 | T91 | 3 | T92 | 3 | T93 | 98 | ||||
auto[1] | 3352 | 1 | T572 | 1 | T557 | 1 | T574 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6881 | 1 | T560 | 1 | T557 | 1 | T574 | 1 | ||||
rising | 6913 | 1 | T560 | 1 | T557 | 1 | T573 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 185595 | 1 | T91 | 5 | T92 | 3 | T93 | 79 | ||||
auto[1] | 10495 | 1 | T560 | 1 | T557 | 1 | T573 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 35441 | 1 | T415 | 610 | T559 | 867 | T577 | 1790 | ||||
rising | 35460 | 1 | T415 | 609 | T559 | 867 | T577 | 1791 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 79858 | 1 | T415 | 1466 | T559 | 1900 | T577 | 4124 | ||||
auto[1] | 68234 | 1 | T415 | 1183 | T559 | 1693 | T577 | 3457 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 21352 | 1 | T415 | 424 | T559 | 511 | T577 | 1104 | ||||
rising | 21337 | 1 | T415 | 424 | T559 | 511 | T577 | 1104 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 120517 | 1 | T415 | 2088 | T559 | 2954 | T577 | 6174 | ||||
auto[1] | 27575 | 1 | T415 | 561 | T559 | 639 | T577 | 1407 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 21352 | 1 | T415 | 424 | T559 | 511 | T577 | 1104 | ||||
rising | 21337 | 1 | T415 | 424 | T559 | 511 | T577 | 1104 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 120517 | 1 | T415 | 2088 | T559 | 2954 | T577 | 6174 | ||||
auto[1] | 27575 | 1 | T415 | 561 | T559 | 639 | T577 | 1407 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4689 | 1 | T415 | 149 | T559 | 89 | T577 | 227 | ||||
rising | 4681 | 1 | T415 | 149 | T559 | 89 | T577 | 227 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 141466 | 1 | T415 | 2400 | T559 | 3483 | T577 | 7251 | ||||
auto[1] | 6626 | 1 | T415 | 249 | T559 | 110 | T577 | 330 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 107932 | 1 | T415 | 1 | T559 | 1 | T406 | 274 | ||||
rising | 107957 | 1 | T415 | 1 | T559 | 1 | T406 | 274 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 38773003 | 1 | T1 | 353 | T2 | 8809 | T3 | 13499 | ||||
auto[1] | 618302 | 1 | T415 | 1 | T559 | 1 | T406 | 378 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 36276 | 1 | T415 | 641 | T559 | 904 | T577 | 1892 | ||||
rising | 36275 | 1 | T415 | 642 | T559 | 904 | T577 | 1891 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 79218 | 1 | T415 | 1488 | T559 | 1905 | T577 | 3980 | ||||
auto[1] | 68874 | 1 | T415 | 1161 | T559 | 1688 | T577 | 3601 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 30868 | 1 | T415 | 566 | T559 | 774 | T577 | 1593 | ||||
rising | 30866 | 1 | T415 | 565 | T559 | 774 | T577 | 1593 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 103865 | 1 | T415 | 1871 | T559 | 2494 | T577 | 5350 | ||||
auto[1] | 44227 | 1 | T415 | 778 | T559 | 1099 | T577 | 2231 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2391 | 1 | T274 | 1 | T568 | 1 | T560 | 1 | ||||
rising | 2410 | 1 | T274 | 1 | T568 | 1 | T560 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 199494 | 1 | T91 | 6 | T92 | 9 | T93 | 94 | ||||
auto[1] | 2519 | 1 | T274 | 1 | T568 | 1 | T560 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3129 | 1 | T274 | 1 | T536 | 1 | T537 | 1 | ||||
rising | 3153 | 1 | T274 | 1 | T536 | 1 | T537 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 189728 | 1 | T91 | 12 | T92 | 3 | T93 | 92 | ||||
auto[1] | 3359 | 1 | T274 | 1 | T536 | 1 | T537 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6372 | 1 | T475 | 1 | T274 | 1 | T536 | 2 | ||||
rising | 6425 | 1 | T475 | 1 | T274 | 1 | T536 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 167633 | 1 | T91 | 5 | T92 | 3 | T93 | 83 | ||||
auto[1] | 24472 | 1 | T475 | 1 | T274 | 1 | T536 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7224 | 1 | T93 | 1 | T537 | 1 | T569 | 1 | ||||
rising | 7285 | 1 | T93 | 1 | T537 | 1 | T569 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 169995 | 1 | T91 | 5 | T92 | 4 | T93 | 87 | ||||
auto[1] | 18984 | 1 | T93 | 1 | T537 | 1 | T569 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2986 | 1 | T563 | 1 | T537 | 1 | T560 | 1 | ||||
rising | 3016 | 1 | T563 | 1 | T537 | 1 | T560 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 181604 | 1 | T91 | 8 | T92 | 7 | T93 | 101 | ||||
auto[1] | 3179 | 1 | T563 | 1 | T537 | 1 | T560 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7965 | 1 | T475 | 1 | T536 | 1 | T537 | 2 | ||||
rising | 8010 | 1 | T475 | 1 | T536 | 1 | T537 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 174604 | 1 | T91 | 7 | T92 | 4 | T93 | 98 | ||||
auto[1] | 17074 | 1 | T475 | 1 | T536 | 1 | T537 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6236 | 1 | T536 | 1 | T557 | 1 | T556 | 1 | ||||
rising | 6267 | 1 | T536 | 1 | T557 | 1 | T556 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 171297 | 1 | T91 | 7 | T92 | 5 | T93 | 106 | ||||
auto[1] | 10509 | 1 | T536 | 1 | T557 | 1 | T556 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5307 | 1 | T274 | 1 | T568 | 1 | T560 | 1 | ||||
rising | 5341 | 1 | T274 | 1 | T568 | 1 | T560 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 185693 | 1 | T91 | 7 | T92 | 6 | T93 | 92 | ||||
auto[1] | 10106 | 1 | T274 | 1 | T568 | 1 | T560 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |