| | | | | | | |
prim_mubi4_dec |
0.00 |
0.00 |
|
|
|
|
|
prim_packer_fifo |
68.93 |
100.00 |
90.00 |
|
|
85.71 |
0.00 |
rv_plic_gateway |
69.17 |
100.00 |
20.00 |
|
|
87.50 |
|
padring |
76.20 |
98.18 |
|
54.21 |
|
|
|
pinmux |
80.29 |
79.59 |
83.85 |
66.69 |
|
79.31 |
92.00 |
pinmux_wkup |
81.33 |
78.95 |
92.31 |
|
|
72.73 |
|
top_earlgrey |
84.10 |
92.47 |
|
59.83 |
|
|
100.00 |
ast |
84.26 |
|
|
84.26 |
|
|
|
otp_ctrl |
84.61 |
|
|
84.61 |
|
|
|
prim_generic_clock_mux2 |
85.19 |
100.00 |
55.56 |
|
|
|
100.00 |
spi_device |
86.57 |
|
|
86.57 |
|
|
|
prim_generic_pad_wrapper |
88.89 |
88.89 |
83.33 |
|
|
83.33 |
100.00 |
prim_generic_pad_wrapper |
100.00 |
|
|
|
|
|
100.00 |
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 ) |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole ) |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 ) |
55.56 |
66.67 |
50.00 |
|
|
50.00 |
|
tlul_adapter_host |
89.09 |
91.11 |
75.79 |
|
|
89.44 |
100.00 |
tlul_adapter_host |
100.00 |
|
|
|
|
|
100.00 |
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 ) |
87.89 |
91.30 |
82.35 |
|
|
90.00 |
|
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 ) |
83.01 |
90.91 |
69.23 |
|
|
88.89 |
|
keymgr |
89.72 |
|
|
89.72 |
|
|
|
rv_core_ibex |
90.02 |
94.12 |
89.29 |
98.53 |
|
100.00 |
68.18 |
lc_ctrl |
90.97 |
|
|
90.97 |
|
|
|
rv_plic |
91.26 |
99.65 |
66.67 |
100.00 |
|
100.00 |
90.00 |
prim_max_tree |
91.58 |
89.27 |
77.06 |
|
|
100.00 |
100.00 |
tlul_rsp_intg_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
66.67 |
66.67 |
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_sync_reqack |
91.67 |
100.00 |
66.67 |
|
|
100.00 |
100.00 |
tlul_err_resp |
91.75 |
95.24 |
80.00 |
|
|
100.00 |
|
chip_earlgrey_asic |
91.90 |
80.00 |
100.00 |
95.71 |
|
|
|
sensor_ctrl |
92.38 |
93.69 |
89.00 |
79.23 |
|
100.00 |
100.00 |
sensor_ctrl_reg_top |
92.41 |
100.00 |
69.65 |
|
|
100.00 |
100.00 |
prim_reg_cdc_arb |
92.91 |
96.00 |
93.02 |
|
|
82.61 |
100.00 |
prim_reg_cdc_arb |
91.30 |
|
|
|
|
82.61 |
100.00 |
prim_reg_cdc_arb ( parameter DataWidth=11,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=9,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 ) |
89.02 |
92.00 |
86.05 |
|
|
|
|
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
i2c |
93.18 |
|
|
93.18 |
|
|
|
tlul_rsp_intg_chk |
93.33 |
100.00 |
80.00 |
|
|
|
100.00 |
ibex_top |
93.34 |
|
|
93.34 |
|
|
|
entropy_src |
93.54 |
|
|
93.54 |
|
|
|
usbdev |
94.12 |
|
|
94.12 |
|
|
|
tlul_socket_1n |
95.64 |
94.64 |
93.18 |
|
|
94.74 |
100.00 |
prim_edn_req |
96.15 |
100.00 |
84.62 |
|
|
100.00 |
100.00 |
prim_generic_usb_diff_rx |
96.30 |
100.00 |
88.89 |
|
|
100.00 |
|
prim_arbiter_fixed |
96.55 |
100.00 |
93.33 |
|
|
100.00 |
92.86 |
usbdev_aon_wake |
96.98 |
100.00 |
93.18 |
|
|
94.74 |
100.00 |
rom_ctrl |
97.19 |
|
|
97.19 |
|
|
|
spi_host |
97.21 |
|
|
97.21 |
|
|
|
prim_reg_cdc |
97.25 |
100.00 |
89.01 |
|
|
100.00 |
100.00 |
prim_reg_cdc |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 ) |
92.31 |
|
92.31 |
|
|
|
|
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=11,ResetVal=0,BitMask=1793,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal=9,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 ) |
85.71 |
|
85.71 |
|
|
|
|
sram_ctrl |
97.94 |
|
|
97.94 |
|
|
|
flash_ctrl |
98.79 |
|
|
98.79 |
|
|
|
kmac |
98.92 |
|
|
98.92 |
|
|
|
otbn |
99.02 |
|
|
99.02 |
|
|
|
pinmux_reg_top |
99.26 |
99.83 |
97.20 |
|
|
100.00 |
100.00 |
csrng |
99.27 |
|
|
99.27 |
|
|
|
edn |
99.34 |
|
|
99.34 |
|
|
|
tlul_adapter_reg |
99.49 |
100.00 |
97.96 |
|
|
100.00 |
100.00 |
pinmux_strap_sampling |
99.83 |
99.34 |
100.00 |
|
|
100.00 |
100.00 |
rv_core_ibex_cfg_reg_top |
99.84 |
100.00 |
99.36 |
|
|
100.00 |
100.00 |
rv_plic_reg_top |
99.98 |
100.00 |
99.90 |
|
|
100.00 |
100.00 |
aes |
100.00 |
|
|
100.00 |
|
|
|
gpio |
100.00 |
|
|
100.00 |
|
|
|
rstmgr |
100.00 |
|
|
100.00 |
|
|
|
adc_ctrl |
100.00 |
|
|
100.00 |
|
|
|
pwm |
100.00 |
|
|
100.00 |
|
|
|
prim_lc_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_lc_sync |
100.00 |
|
|
|
|
|
100.00 |
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_lc_sender |
100.00 |
100.00 |
|
|
|
|
|
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
hmac |
100.00 |
|
|
100.00 |
|
|
|
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
tlul_cmd_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
tlul_fifo_sync |
100.00 |
|
100.00 |
|
|
100.00 |
|
prim_edge_detector |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
clk_ctrl_and_main_pd_sva_if |
100.00 |
|
|
100.00 |
|
|
|
rv_dm |
100.00 |
|
|
100.00 |
|
|
|
prim_subreg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=3,RESVAL,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=4,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL,Mubi=0 + DW=3,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=32,SwAccess=1,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi + DW=32,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL,Mubi + DW=4,SwAccess=1,RESVAL=0,Mubi=0 + DW=4,SwAccess=3,RESVAL=9,Mubi=1 + DW=4,SwAccess=4,RESVAL=9,Mubi=1 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=6,SwAccess=0,RESVAL,Mubi=0 + DW=6,SwAccess=1,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=7,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 + DW=8,SwAccess=1,RESVAL,Mubi=0 + DW=8,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
pinmux_jtag_breakout |
100.00 |
100.00 |
|
100.00 |
|
|
|
prim_lc_or_hardened |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
prim_intr_hw |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_pulse_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_fifo_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_subreg_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=32,SwAccess=3,Mubi=0 + DW=3,SwAccess=3,Mubi=0 + DW=10,SwAccess=3,Mubi=0 + DW=5,SwAccess=3,Mubi=0 + DW=8,SwAccess=3,Mubi=0 + DW=2,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=4,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 + DW=16,SwAccess=5,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 + DW=1,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=1 + DW=12,SwAccess=0,Mubi=0 + DW=13,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=30,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=20,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 + DW=6,SwAccess=0,Mubi=0 + DW=11,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 + DW=27,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=1,Mubi=0 + DW=1,SwAccess=1,Mubi=0 + DW=5,SwAccess=1,Mubi=0 + DW=9,SwAccess=1,Mubi=0 + DW=8,SwAccess=1,Mubi=0 + DW=3,SwAccess=1,Mubi=0 + DW=6,SwAccess=1,Mubi=0 + DW=4,SwAccess=1,Mubi=0 + DW=2,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 + DW=20,SwAccess=1,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=4,SwAccess=4,Mubi=1 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=6,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
clkmgr |
100.00 |
|
|
100.00 |
|
|
|
aon_timer |
100.00 |
|
|
100.00 |
|
|
|
pattgen |
100.00 |
|
|
100.00 |
|
|
|
sysrst_ctrl |
100.00 |
|
|
100.00 |
|
|
|
uart |
100.00 |
|
|
100.00 |
|
|
|
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
alert_handler |
100.00 |
|
|
100.00 |
|
|
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
xbar_main |
100.00 |
|
|
100.00 |
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
pwrmgr |
100.00 |
|
|
100.00 |
|
|
|
prim_esc_receiver |
100.00 |
|
|
100.00 |
|
|
|
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
xbar_peri |
100.00 |
|
|
100.00 |
|
|
|
prim_sync_reqack_data |
100.00 |
100.00 |
|
|
|
|
100.00 |
rv_timer |
100.00 |
|
|
100.00 |
|
|
|
rv_core_addr_trans |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
rv_plic_target |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_mubi4_sync |
100.00 |
|
|
|
|
|
100.00 |
prim_generic_clock_buf |
100.00 |
100.00 |
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|
|
pinmux_jtag_buf |
|
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|
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prim_usb_diff_rx |
|
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prim_clock_buf |
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tlul_data_integ_enc |
|
|
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prim_reg_we_check |
|
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